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https://github.com/c64scene-ar/llvm-6502.git
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Add partial word version of ATOMIC_SWAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
parent
667d8f7607
commit
0e55f0678c
@ -3855,6 +3855,7 @@ SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
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MachineBasicBlock *
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PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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bool is64bit, unsigned BinOpcode) {
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// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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@ -3874,7 +3875,8 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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exitMBB->transferSuccessors(BB);
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MachineRegisterInfo &RegInfo = F->getRegInfo();
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unsigned TmpReg = RegInfo.createVirtualRegister(
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unsigned TmpReg = (!BinOpcode) ? incr :
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RegInfo.createVirtualRegister(
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is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
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(const TargetRegisterClass *) &PPC::G8RCRegClass);
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@ -3892,6 +3894,7 @@ PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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BB = loopMBB;
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BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
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.addReg(ptrA).addReg(ptrB);
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if (BinOpcode)
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BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
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BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
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.addReg(TmpReg).addReg(ptrA).addReg(ptrB);
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@ -3911,6 +3914,7 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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MachineBasicBlock *BB,
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bool is8bit, // operation
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unsigned BinOpcode) {
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// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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// In 64 bit mode we have to use 64 bits for addresses, even though the
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// lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
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@ -3938,7 +3942,6 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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const TargetRegisterClass *RC =
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is64bit ? (const TargetRegisterClass *) &PPC::GPRCRegClass :
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(const TargetRegisterClass *) &PPC::G8RCRegClass;
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unsigned TmpReg = RegInfo.createVirtualRegister(RC);
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unsigned PtrReg = RegInfo.createVirtualRegister(RC);
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unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
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unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
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@ -3949,7 +3952,9 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
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unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
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unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
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unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
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unsigned Ptr1Reg;
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unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
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// thisMBB:
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// ...
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@ -3966,14 +3971,15 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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// li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
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// slw mask, mask2, shift
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// loopMBB:
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// l[wd]arx dest, ptr
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// add tmp, dest, incr2
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// andc tmp2, dest, mask
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// l[wd]arx tmpDest, ptr
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// add tmp, tmpDest, incr2
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// andc tmp2, tmpDest, mask
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// and tmp3, tmp, mask
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// or tmp4, tmp3, tmp2
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// st[wd]cx. tmp4, ptr
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// bne- loopMBB
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// fallthrough --> exitMBB
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// srw dest, tmpDest, shift
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if (ptrA!=PPC::R0) {
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Ptr1Reg = RegInfo.createVirtualRegister(RC);
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@ -4004,11 +4010,13 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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.addReg(Mask2Reg).addReg(ShiftReg);
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BB = loopMBB;
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BuildMI(BB, TII->get(PPC::LWARX), dest)
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BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
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.addReg(PPC::R0).addReg(PtrReg);
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BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(Incr2Reg).addReg(dest);
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if (BinOpcode)
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BuildMI(BB, TII->get(BinOpcode), TmpReg)
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.addReg(Incr2Reg).addReg(TmpDestReg);
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BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
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.addReg(dest).addReg(MaskReg);
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.addReg(TmpDestReg).addReg(MaskReg);
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BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
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.addReg(TmpReg).addReg(MaskReg);
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BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
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@ -4023,6 +4031,7 @@ PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
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// exitMBB:
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// ...
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BB = exitMBB;
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BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
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return BB;
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}
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@ -4140,6 +4149,15 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
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BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
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else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
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BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
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else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
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BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
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else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
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BB = EmitAtomicBinary(MI, BB, false, 0);
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else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
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BB = EmitAtomicBinary(MI, BB, true, 0);
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else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
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MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
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bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
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@ -4204,45 +4222,6 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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// ...
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BB = exitMBB;
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}
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else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32 ||
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MI->getOpcode() == PPC::ATOMIC_SWAP_I64) {
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bool is64bit = MI->getOpcode() == PPC::ATOMIC_SWAP_I64;
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptrA = MI->getOperand(1).getReg();
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unsigned ptrB = MI->getOperand(2).getReg();
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unsigned newval = MI->getOperand(3).getReg();
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MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
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F->insert(It, loopMBB);
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F->insert(It, exitMBB);
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exitMBB->transferSuccessors(BB);
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// thisMBB:
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// ...
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// fallthrough --> loopMBB
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BB->addSuccessor(loopMBB);
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// loopMBB:
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// l[wd]arx dest, ptr
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// st[wd]cx. newval, ptr
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// bne- loopMBB
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// fallthrough --> exitMBB
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BB = loopMBB;
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BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
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.addReg(ptrA).addReg(ptrB);
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BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
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.addReg(newval).addReg(ptrA).addReg(ptrB);
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BuildMI(BB, TII->get(PPC::BCC))
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.addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
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BB->addSuccessor(loopMBB);
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BB->addSuccessor(exitMBB);
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// exitMBB:
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// ...
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BB = exitMBB;
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}
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else {
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assert(0 && "Unexpected instr type to insert");
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}
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