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Fix a false error reported by the tblgen backend for machine model
"ProcResource def is not included in the ProcResources". Some of the machine model definitions were not added to the processor's list used for diagnostics and error checking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203749 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1473,11 +1473,23 @@ void CodeGenSchedModels::collectProcResources() {
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Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
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addWriteRes(*WRI, getProcModel(ModelDef).Index);
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}
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RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");
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for (RecIter WRI = SWRDefs.begin(), WRE = SWRDefs.end(); WRI != WRE; ++WRI) {
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Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
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addWriteRes(*WRI, getProcModel(ModelDef).Index);
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}
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RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");
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for (RecIter RAI = RADefs.begin(), RAE = RADefs.end(); RAI != RAE; ++RAI) {
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Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
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addReadAdvance(*RAI, getProcModel(ModelDef).Index);
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}
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RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");
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for (RecIter RAI = SRADefs.begin(), RAE = SRADefs.end(); RAI != RAE; ++RAI) {
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if ((*RAI)->getValueInit("SchedModel")->isComplete()) {
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Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
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addReadAdvance(*RAI, getProcModel(ModelDef).Index);
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}
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}
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// Add ProcResGroups that are defined within this processor model, which may
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// not be directly referenced but may directly specify a buffer size.
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RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");
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