6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-22 10:24:26 +00:00
Code Issues Projects Releases Wiki Activity

Fix a false error reported by the tblgen backend for machine model

Browse Source 
"ProcResource def is not included in the ProcResources".

Some of the machine model definitions were not added to the
processor's list used for diagnostics and error checking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203749 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2014-03-13 03:49:20 +00:00
parent ce5a6548a2
commit 0e8c89ae8f
1 changed files with 12 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
utils/TableGen/CodeGenSchedule.cpp
View File

@ -1473,11 +1473,23 @@ void CodeGenSchedModels::collectProcResources() {
Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
addWriteRes(*WRI, getProcModel(ModelDef).Index);
}
RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");
for (RecIter WRI = SWRDefs.begin(), WRE = SWRDefs.end(); WRI != WRE; ++WRI) {
Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
addWriteRes(*WRI, getProcModel(ModelDef).Index);
}
RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");
for (RecIter RAI = RADefs.begin(), RAE = RADefs.end(); RAI != RAE; ++RAI) {
Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
addReadAdvance(*RAI, getProcModel(ModelDef).Index);
}
RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");
for (RecIter RAI = SRADefs.begin(), RAE = SRADefs.end(); RAI != RAE; ++RAI) {
if ((*RAI)->getValueInit("SchedModel")->isComplete()) {
Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
addReadAdvance(*RAI, getProcModel(ModelDef).Index);
}
}
// Add ProcResGroups that are defined within this processor model, which may
// not be directly referenced but may directly specify a buffer size.
RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");