diff --git a/lib/Target/PowerPC/PPC32AsmPrinter.cpp b/lib/Target/PowerPC/PPC32AsmPrinter.cpp index 46778259841..fb3e1824e73 100644 --- a/lib/Target/PowerPC/PPC32AsmPrinter.cpp +++ b/lib/Target/PowerPC/PPC32AsmPrinter.cpp @@ -89,6 +89,8 @@ namespace { if (MO.getType() == MachineOperand::MO_MachineRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name); + } else if (MO.isImmediate()) { + O << MO.getImmedValue(); } else { printOp(MO); } diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 46778259841..fb3e1824e73 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -89,6 +89,8 @@ namespace { if (MO.getType() == MachineOperand::MO_MachineRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name); + } else if (MO.isImmediate()) { + O << MO.getImmedValue(); } else { printOp(MO); } diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 4c0a913d8ee..c0930e79fe3 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -18,7 +18,6 @@ def Pseudo: Format<0>; def Gpr : Format<1>; def Gpr0 : Format<2>; def Simm16 : Format<3>; -def Zimm16 : Format<4>; def PCRelimm24 : Format<5>; def Imm24 : Format<6>; def Imm5 : Format<7>; @@ -152,8 +151,8 @@ class DForm_4 opcode, bit ppc64, bit vmx, let AsmString = asmstr; } -class DForm_4_zero opcode, bit ppc64, bit vmx> - : DForm_1 { +class DForm_4_zero opcode, bit ppc64, bit vmx, + dag OL, string asmstr> : DForm_1<"", opcode, ppc64, vmx> { let ArgCount = 0; let Arg0Type = 0; let Arg1Type = 0; @@ -161,6 +160,8 @@ class DForm_4_zero opcode, bit ppc64, bit vmx> let A = 0; let B = 0; let C = 0; + let OperandList = OL; + let AsmString = asmstr; } class DForm_5 opcode, bit ppc64, bit vmx> @@ -194,13 +195,16 @@ class DForm_5_ext opcode, bit ppc64, bit vmx> let Arg3Type = 0; } -class DForm_6 opcode, bit ppc64, bit vmx> - : DForm_5 { - let Arg3Type = Zimm16.Value; +class DForm_6 opcode, bit ppc64, bit vmx, + dag OL, string asmstr> + : DForm_5<"", opcode, ppc64, vmx> { + let OperandList = OL; + let AsmString = asmstr; } -class DForm_6_ext opcode, bit ppc64, bit vmx> - : DForm_6 { +class DForm_6_ext opcode, bit ppc64, bit vmx, + dag OL, string asmstr> + : DForm_6 { let L = ppc64; let ArgCount = 3; let Arg0Type = Imm3.Value; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 47e250a5888..3631ef6d62e 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -85,9 +85,15 @@ def CMPDI : DForm_5_ext<"cmpdi", 11, 1, 0>; def CMP : XForm_16<"cmp", 31, 0, 0, 0>; def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>; def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>; -def CMPLI : DForm_6<"cmpli", 10, 0, 0>; -def CMPLWI : DForm_6_ext<"cmplwi", 10, 0, 0>; -def CMPLDI : DForm_6_ext<"cmpldi", 10, 1, 0>; +def CMPLI : DForm_6<10, 0, 0, + (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2), + "cmpli $dst, $size, $src1, $src2">; +def CMPLWI : DForm_6_ext<10, 0, 0, + (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), + "cmplwi $dst, $src1, $src2">; +def CMPLDI : DForm_6_ext<10, 1, 0, + (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), + "cmpldi $dst, $src1, $src2">; def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>; def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>; def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>; @@ -144,7 +150,7 @@ def MULHWU : XOForm_2<"mulhwu", 31, 11, 0, 0, 0>; def NAND : XForm_6<"nand", 31, 476, 0, 0, 0>; def NEG : XOForm_3<"neg", 31, 104, 0, 0, 0, 0>; def NOR : XForm_6<"nor", 31, 124, 0, 0, 0>; -def NOP : DForm_4_zero<"nop", 24, 0, 0>; +def NOP : DForm_4_zero<"nop", 24, 0, 0, (ops), "nop">; def ORI : DForm_4<24, 0, 0, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), "ori $dst, $src1, $src2">;