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Add instruction encodings / disassembly support for u10 / lu10 instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-01-22 22:55:04 +00:00
parent 7ad70bf46a
commit 0ec35ac4fc
3 changed files with 36 additions and 12 deletions
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14
lib/Target/XCore/XCoreInstrFormats.td
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@ -125,12 +125,22 @@ class _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{9-0} = a{15-6}; let Inst{9-0} = a{15-6};
} }
class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern> class _FU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<2, outs, ins, asmstr, pattern> { : InstXCore<2, outs, ins, asmstr, pattern> {
bits<10> a;
let Inst{15-10} = opc;
let Inst{9-0} = a;
} }
class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern> class _FLU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> { : InstXCore<4, outs, ins, asmstr, pattern> {
bits<20> a;
let Inst{31-26} = opc;
let Inst{25-16} = a{9-0};
let Inst{15-10} = 0b111100;
let Inst{9-0} = a{19-10};
} }
class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>

20
lib/Target/XCore/XCoreInstrInfo.td
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@ -649,24 +649,24 @@ defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
// TODO ldwcpl, blacp // TODO ldwcpl, blacp
let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
def LDAPF_u10 : _FU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", []>; def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>;
let Defs = [R11], isReMaterializable = 1 in let Defs = [R11], isReMaterializable = 1 in
def LDAPF_lu10 : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
[(set R11, (pcrelwrapper tglobaladdr:$addr))]>; [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
let Defs = [R11], isReMaterializable = 1 in let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in
def LDAPF_lu10_ba : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
[(set R11, (pcrelwrapper tblockaddress:$addr))]>; [(set R11, (pcrelwrapper tblockaddress:$a))]>;
let isCall=1, let isCall=1,
// All calls clobber the link register and the non-callee-saved registers: // All calls clobber the link register and the non-callee-saved registers:
Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
def BLRF_u10 : _FU10<(outs), (ins calltarget:$target), "bl $target", def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
[(XCoreBranchLink immU10:$target)]>; [(XCoreBranchLink immU10:$a)]>;
def BLRF_lu10 : _FLU10<(outs), (ins calltarget:$target), "bl $target", def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
[(XCoreBranchLink immU20:$target)]>; [(XCoreBranchLink immU20:$a)]>;
} }
// Two operand short // Two operand short

14
test/MC/Disassembler/XCore/xcore.txt
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@ -442,3 +442,17 @@
# CHECK: setsr 21863 # CHECK: setsr 21863
0x55 0xf1 0x67 0x7b 0x55 0xf1 0x67 0x7b
# u10 / lu10 instructions
# CHECK: ldap r11, 40
0x28 0xd8
# CHECK: ldap r11, 53112
0x33 0xf0 0x78 0xdb
# CHECK: bl 8
0x08 0xd0
# CHECK: bl 38631
0x25 0xf0 0xe7 0xd2