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Add instruction encodings / disassembly support for u10 / lu10 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -125,12 +125,22 @@ class _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let Inst{9-0} = a{15-6};
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let Inst{9-0} = a{15-6};
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}
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}
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class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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: InstXCore<2, outs, ins, asmstr, pattern> {
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bits<10> a;
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let Inst{15-10} = opc;
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let Inst{9-0} = a;
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}
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}
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class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FLU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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: InstXCore<4, outs, ins, asmstr, pattern> {
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bits<20> a;
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let Inst{31-26} = opc;
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let Inst{25-16} = a{9-0};
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let Inst{15-10} = 0b111100;
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let Inst{9-0} = a{19-10};
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}
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}
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class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -649,24 +649,24 @@ defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
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// TODO ldwcpl, blacp
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// TODO ldwcpl, blacp
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let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
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let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
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def LDAPF_u10 : _FU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", []>;
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def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>;
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let Defs = [R11], isReMaterializable = 1 in
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let Defs = [R11], isReMaterializable = 1 in
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def LDAPF_lu10 : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr",
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def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
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[(set R11, (pcrelwrapper tglobaladdr:$addr))]>;
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[(set R11, (pcrelwrapper tglobaladdr:$a))]>;
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let Defs = [R11], isReMaterializable = 1 in
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let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in
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def LDAPF_lu10_ba : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr",
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def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
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[(set R11, (pcrelwrapper tblockaddress:$addr))]>;
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[(set R11, (pcrelwrapper tblockaddress:$a))]>;
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let isCall=1,
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let isCall=1,
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// All calls clobber the link register and the non-callee-saved registers:
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// All calls clobber the link register and the non-callee-saved registers:
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Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
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Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
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def BLRF_u10 : _FU10<(outs), (ins calltarget:$target), "bl $target",
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def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
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[(XCoreBranchLink immU10:$target)]>;
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[(XCoreBranchLink immU10:$a)]>;
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def BLRF_lu10 : _FLU10<(outs), (ins calltarget:$target), "bl $target",
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def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
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[(XCoreBranchLink immU20:$target)]>;
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[(XCoreBranchLink immU20:$a)]>;
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}
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}
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// Two operand short
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// Two operand short
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@ -442,3 +442,17 @@
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# CHECK: setsr 21863
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# CHECK: setsr 21863
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0x55 0xf1 0x67 0x7b
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0x55 0xf1 0x67 0x7b
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# u10 / lu10 instructions
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# CHECK: ldap r11, 40
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0x28 0xd8
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# CHECK: ldap r11, 53112
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0x33 0xf0 0x78 0xdb
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# CHECK: bl 8
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0x08 0xd0
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# CHECK: bl 38631
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0x25 0xf0 0xe7 0xd2
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