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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Adding unsigned halfword load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224772 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
e5fa612e9e
commit
0ece0ce8cd
@ -607,7 +607,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
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else
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Opcode = zextval ? Hexagon::LDriuh : Hexagon::LDrih;
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Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::LDrih;
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} else if (LoadedVT == MVT::i8) {
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if (TII->isValidAutoIncImm(LoadedVT, Val))
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Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;
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@ -679,9 +679,8 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
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return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
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case Hexagon::LDrih:
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case Hexagon::LDriuh:
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case Hexagon::L2_loadruh_io:
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case Hexagon::LDrih_indexed:
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case Hexagon::LDriuh_indexed:
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return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
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case Hexagon::L2_loadrb_io:
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@ -1124,7 +1123,7 @@ isValidOffset(const int Opcode, const int Offset) const {
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(Offset <= Hexagon_MEMD_OFFSET_MAX);
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case Hexagon::LDrih:
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case Hexagon::LDriuh:
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case Hexagon::L2_loadruh_io:
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case Hexagon::STrih:
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return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
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(Offset <= Hexagon_MEMH_OFFSET_MAX);
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@ -1364,10 +1363,8 @@ isConditionalLoad (const MachineInstr* MI) const {
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case Hexagon::LDrih_indexed_cNotPt :
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case Hexagon::L2_ploadrbt_io:
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case Hexagon::L2_ploadrbf_io:
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case Hexagon::LDriuh_cPt :
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case Hexagon::LDriuh_cNotPt :
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case Hexagon::LDriuh_indexed_cPt :
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case Hexagon::LDriuh_indexed_cNotPt :
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case Hexagon::L2_ploadruht_io:
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case Hexagon::L2_ploadruhf_io:
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case Hexagon::L2_ploadrubt_io:
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case Hexagon::L2_ploadrubf_io:
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return true;
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@ -1547,6 +1547,10 @@ let accessSize = ByteAccess, isCodeGenOnly = 0 in {
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defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
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}
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let accessSize = HalfWordAccess, opExtentAlign = 1 in {
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defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
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}
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///
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// Load -- MEMri operand
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multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
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@ -1589,7 +1593,6 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
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let addrMode = BaseImmOffset, isMEMri = "true" in {
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let accessSize = HalfWordAccess in {
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defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
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defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
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}
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let accessSize = WordAccess in
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@ -1609,7 +1612,7 @@ def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
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(LDrih ADDRriS11_1:$addr) >;
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def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
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(LDriuh ADDRriS11_1:$addr) >;
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(L2_loadrub_io AddrFI:$addr, 0) >;
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def : Pat < (i32 (load ADDRriS11_2:$addr)),
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(LDriw ADDRriS11_2:$addr) >;
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@ -1662,8 +1665,6 @@ let addrMode = BaseImmOffset in {
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let accessSize = HalfWordAccess in {
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defm LDrih_indexed: LD_Idxd2 <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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defm LDriuh_indexed: LD_Idxd2 <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
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12, 7>, AddrModeRel;
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}
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let accessSize = WordAccess in
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defm LDriw_indexed: LD_Idxd2 <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
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@ -1685,7 +1686,7 @@ def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
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(LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
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def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
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(LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
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(L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >;
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def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
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(LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
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@ -3661,10 +3662,10 @@ def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
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// 16 bit atomic load
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def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
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(i32 (LDriuh ADDRriS11_1:$src1))>;
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(i32 (L2_loadruh_io AddrFI:$src1, 0))>;
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def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
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(i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
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(i32 (L2_loadruh_io (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
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def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
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(i32 (LDriw ADDRriS11_2:$src1))>;
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@ -4078,13 +4079,13 @@ def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
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// i16 -> i64
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def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
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(i64 (A2_combinew (A2_tfrsi 0), (LDriuh ADDRriS11_1:$src1)))>,
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(i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
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Requires<[NoV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
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s11_1ExtPred:$offset))),
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(i64 (A2_combinew (A2_tfrsi 0), (LDriuh_indexed IntRegs:$src1,
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(i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
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s11_1ExtPred:$offset)))>,
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Requires<[NoV4T]>;
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@ -436,13 +436,13 @@ def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
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// zext i16->i64
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def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
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(i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>,
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(i64 (COMBINE_Ir_V4 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
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Requires<[HasV4T]>;
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let AddedComplexity = 20 in
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def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
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s11_1ExtPred:$offset))),
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(i64 (COMBINE_Ir_V4 0, (LDriuh_indexed IntRegs:$src1,
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(i64 (COMBINE_Ir_V4 0, (L2_loadruh_io IntRegs:$src1,
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s11_1ExtPred:$offset)))>,
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Requires<[HasV4T]>;
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@ -162,7 +162,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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if ( (MI.getOpcode() == Hexagon::LDriw) ||
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(MI.getOpcode() == Hexagon::LDrid) ||
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(MI.getOpcode() == Hexagon::LDrih) ||
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(MI.getOpcode() == Hexagon::LDriuh) ||
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(MI.getOpcode() == Hexagon::L2_loadruh_io) ||
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(MI.getOpcode() == Hexagon::L2_loadrb_io) ||
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(MI.getOpcode() == Hexagon::L2_loadrub_io) ||
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(MI.getOpcode() == Hexagon::LDriw_f) ||
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