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[Hexagon] Adding unsigned halfword load.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224772 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-23 16:42:57 +00:00
parent e5fa612e9e
commit 0ece0ce8cd
5 changed files with 18 additions and 20 deletions
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2
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -607,7 +607,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih; Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;
else else
Opcode = zextval ? Hexagon::LDriuh : Hexagon::LDrih; Opcode = zextval ? Hexagon::L2_loadruh_io : Hexagon::LDrih;
} else if (LoadedVT == MVT::i8) { } else if (LoadedVT == MVT::i8) {
if (TII->isValidAutoIncImm(LoadedVT, Val)) if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib; Opcode = zextval ? Hexagon::POST_LDriub : Hexagon::POST_LDrib;

11
lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -679,9 +679,8 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
return isShiftedUInt<6,2>(MI->getOperand(2).getImm()); return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
case Hexagon::LDrih: case Hexagon::LDrih:
case Hexagon::LDriuh: case Hexagon::L2_loadruh_io:
case Hexagon::LDrih_indexed: case Hexagon::LDrih_indexed:
case Hexagon::LDriuh_indexed:
return isShiftedUInt<6,1>(MI->getOperand(2).getImm()); return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
case Hexagon::L2_loadrb_io: case Hexagon::L2_loadrb_io:
@ -1124,7 +1123,7 @@ isValidOffset(const int Opcode, const int Offset) const {
(Offset <= Hexagon_MEMD_OFFSET_MAX); (Offset <= Hexagon_MEMD_OFFSET_MAX);
case Hexagon::LDrih: case Hexagon::LDrih:
case Hexagon::LDriuh: case Hexagon::L2_loadruh_io:
case Hexagon::STrih: case Hexagon::STrih:
return (Offset >= Hexagon_MEMH_OFFSET_MIN) && return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
(Offset <= Hexagon_MEMH_OFFSET_MAX); (Offset <= Hexagon_MEMH_OFFSET_MAX);
@ -1364,10 +1363,8 @@ isConditionalLoad (const MachineInstr* MI) const {
case Hexagon::LDrih_indexed_cNotPt : case Hexagon::LDrih_indexed_cNotPt :
case Hexagon::L2_ploadrbt_io: case Hexagon::L2_ploadrbt_io:
case Hexagon::L2_ploadrbf_io: case Hexagon::L2_ploadrbf_io:
case Hexagon::LDriuh_cPt : case Hexagon::L2_ploadruht_io:
case Hexagon::LDriuh_cNotPt : case Hexagon::L2_ploadruhf_io:
case Hexagon::LDriuh_indexed_cPt :
case Hexagon::LDriuh_indexed_cNotPt :
case Hexagon::L2_ploadrubt_io: case Hexagon::L2_ploadrubt_io:
case Hexagon::L2_ploadrubf_io: case Hexagon::L2_ploadrubf_io:
return true; return true;

19
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -1547,6 +1547,10 @@ let accessSize = ByteAccess, isCodeGenOnly = 0 in {
defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>; defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>;
} }
let accessSize = HalfWordAccess, opExtentAlign = 1 in {
defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
}
/// ///
// Load -- MEMri operand // Load -- MEMri operand
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC, multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
@ -1589,7 +1593,6 @@ multiclass LD_MEMri<string mnemonic, string CextOp, RegisterClass RC,
let addrMode = BaseImmOffset, isMEMri = "true" in { let addrMode = BaseImmOffset, isMEMri = "true" in {
let accessSize = HalfWordAccess in { let accessSize = HalfWordAccess in {
defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel; defm LDrih: LD_MEMri < "memh", "LDrih", IntRegs, 12, 7>, AddrModeRel;
defm LDriuh: LD_MEMri < "memuh", "LDriuh", IntRegs, 12, 7>, AddrModeRel;
} }
let accessSize = WordAccess in let accessSize = WordAccess in
@ -1609,7 +1612,7 @@ def : Pat < (i32 (sextloadi16 ADDRriS11_1:$addr)),
(LDrih ADDRriS11_1:$addr) >; (LDrih ADDRriS11_1:$addr) >;
def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)), def : Pat < (i32 (zextloadi16 ADDRriS11_1:$addr)),
(LDriuh ADDRriS11_1:$addr) >; (L2_loadrub_io AddrFI:$addr, 0) >;
def : Pat < (i32 (load ADDRriS11_2:$addr)), def : Pat < (i32 (load ADDRriS11_2:$addr)),
(LDriw ADDRriS11_2:$addr) >; (LDriw ADDRriS11_2:$addr) >;
@ -1662,8 +1665,6 @@ let addrMode = BaseImmOffset in {
let accessSize = HalfWordAccess in { let accessSize = HalfWordAccess in {
defm LDrih_indexed: LD_Idxd2 <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, defm LDrih_indexed: LD_Idxd2 <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext,
12, 7>, AddrModeRel; 12, 7>, AddrModeRel;
defm LDriuh_indexed: LD_Idxd2 <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext,
12, 7>, AddrModeRel;
} }
let accessSize = WordAccess in let accessSize = WordAccess in
defm LDriw_indexed: LD_Idxd2 <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, defm LDriw_indexed: LD_Idxd2 <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,
@ -1685,7 +1686,7 @@ def : Pat < (i32 (sextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
(LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >; (LDrih_indexed IntRegs:$src1, s11_1ExtPred:$offset) >;
def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))), def : Pat < (i32 (zextloadi16 (add IntRegs:$src1, s11_1ExtPred:$offset))),
(LDriuh_indexed IntRegs:$src1, s11_1ExtPred:$offset) >; (L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >;
def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))), def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),
(LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >; (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;
@ -3661,10 +3662,10 @@ def : Pat<(atomic_load_8 (add (i32 IntRegs:$src1), s11_0ImmPred:$offset)),
// 16 bit atomic load // 16 bit atomic load
def : Pat<(atomic_load_16 ADDRriS11_1:$src1), def : Pat<(atomic_load_16 ADDRriS11_1:$src1),
(i32 (LDriuh ADDRriS11_1:$src1))>; (i32 (L2_loadruh_io AddrFI:$src1, 0))>;
def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)), def : Pat<(atomic_load_16 (add (i32 IntRegs:$src1), s11_1ImmPred:$offset)),
(i32 (LDriuh_indexed (i32 IntRegs:$src1), s11_1ImmPred:$offset))>; (i32 (L2_loadruh_io (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;
def : Pat<(atomic_load_32 ADDRriS11_2:$src1), def : Pat<(atomic_load_32 ADDRriS11_2:$src1),
(i32 (LDriw ADDRriS11_2:$src1))>; (i32 (LDriw ADDRriS11_2:$src1))>;
@ -4078,13 +4079,13 @@ def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
// i16 -> i64 // i16 -> i64
def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)), def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
(i64 (A2_combinew (A2_tfrsi 0), (LDriuh ADDRriS11_1:$src1)))>, (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io AddrFI:$src1, 0)))>,
Requires<[NoV4T]>; Requires<[NoV4T]>;
let AddedComplexity = 20 in let AddedComplexity = 20 in
def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1), def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
s11_1ExtPred:$offset))), s11_1ExtPred:$offset))),
(i64 (A2_combinew (A2_tfrsi 0), (LDriuh_indexed IntRegs:$src1, (i64 (A2_combinew (A2_tfrsi 0), (L2_loadruh_io IntRegs:$src1,
s11_1ExtPred:$offset)))>, s11_1ExtPred:$offset)))>,
Requires<[NoV4T]>; Requires<[NoV4T]>;

4
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -436,13 +436,13 @@ def: Pat <(i64 (zextloadi1 (add (i32 IntRegs:$src1),
// zext i16->i64 // zext i16->i64
def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)), def: Pat <(i64 (zextloadi16 ADDRriS11_1:$src1)),
(i64 (COMBINE_Ir_V4 0, (LDriuh ADDRriS11_1:$src1)))>, (i64 (COMBINE_Ir_V4 0, (L2_loadruh_io AddrFI:$src1, 0)))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;
let AddedComplexity = 20 in let AddedComplexity = 20 in
def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1), def: Pat <(i64 (zextloadi16 (add (i32 IntRegs:$src1),
s11_1ExtPred:$offset))), s11_1ExtPred:$offset))),
(i64 (COMBINE_Ir_V4 0, (LDriuh_indexed IntRegs:$src1, (i64 (COMBINE_Ir_V4 0, (L2_loadruh_io IntRegs:$src1,
s11_1ExtPred:$offset)))>, s11_1ExtPred:$offset)))>,
Requires<[HasV4T]>; Requires<[HasV4T]>;

2
lib/Target/Hexagon/HexagonRegisterInfo.cpp
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@ -162,7 +162,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
if ( (MI.getOpcode() == Hexagon::LDriw) || if ( (MI.getOpcode() == Hexagon::LDriw) ||
(MI.getOpcode() == Hexagon::LDrid) || (MI.getOpcode() == Hexagon::LDrid) ||
(MI.getOpcode() == Hexagon::LDrih) || (MI.getOpcode() == Hexagon::LDrih) ||
(MI.getOpcode() == Hexagon::LDriuh) || (MI.getOpcode() == Hexagon::L2_loadruh_io) ||
(MI.getOpcode() == Hexagon::L2_loadrb_io) || (MI.getOpcode() == Hexagon::L2_loadrb_io) ||
(MI.getOpcode() == Hexagon::L2_loadrub_io) || (MI.getOpcode() == Hexagon::L2_loadrub_io) ||
(MI.getOpcode() == Hexagon::LDriw_f) || (MI.getOpcode() == Hexagon::LDriw_f) ||