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Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.

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Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2012-05-07 03:13:22 +00:00
parent 3ccbd47ecb
commit 0ed1f764f4
1 changed files with 4 additions and 2 deletions
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6
lib/Target/Mips/MipsISelLowering.cpp
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@ -3056,8 +3056,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
case 'r':
if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
return std::make_pair(0U, &Mips::CPURegsRegClass);
assert(VT == MVT::i64 && "Unexpected type.");
return std::make_pair(0U, &Mips::CPU64RegsRegClass);
if (VT == MVT::i64 && HasMips64)
return std::make_pair(0U, &Mips::CPU64RegsRegClass);
// This will generate an error message
return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
case 'f':
if (VT == MVT::f32)
return std::make_pair(0U, &Mips::FGR32RegClass);