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https://github.com/c64scene-ar/llvm-6502.git
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Use 'array_lengthof' as possible to avoid magic numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao
parent
48b809e6e5
commit
0ee17006b1
@ -1803,7 +1803,8 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
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SDValue Ops[] = { Chain, InFlag };
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Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
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MVT::Other, MVT::Glue, Ops, 2), 1);
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MVT::Other, MVT::Glue, Ops,
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array_lengthof(Ops)), 1);
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Val = Chain.getValue(0);
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// Round the f80 to the right size, which also moves it to the appropriate
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@ -4422,13 +4423,15 @@ static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
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if (Subtarget->hasInt256()) { // AVX2
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SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
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SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
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array_lengthof(Ops));
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} else {
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// 256-bit logic and arithmetic instructions in AVX are all
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// floating-point, no support for integer ops. Emit fp zeroed vectors.
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SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
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SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
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array_lengthof(Ops));
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}
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} else
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llvm_unreachable("Unexpected vector type");
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@ -4449,7 +4452,8 @@ static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
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if (VT.is256BitVector()) {
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if (HasInt256) { // AVX2
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SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
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array_lengthof(Ops));
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} else { // AVX
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Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
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Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
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@ -5119,7 +5123,8 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
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SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
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SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
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SDValue ResNode =
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DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
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DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
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array_lengthof(Ops), MVT::i64,
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LDBase->getPointerInfo(),
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LDBase->getAlignment(),
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false/*isVolatile*/, true/*ReadMem*/,
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@ -7642,10 +7647,10 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
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if (InFlag) {
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SDValue Ops[] = { Chain, TGA, *InFlag };
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Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
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Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
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} else {
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SDValue Ops[] = { Chain, TGA };
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Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
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Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
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}
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// TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
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@ -7955,7 +7960,7 @@ SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
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}
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SDValue Ops[2] = { Lo, Hi };
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return DAG.getMergeValues(Ops, 2, dl);
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return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
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}
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SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
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@ -8238,8 +8243,8 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
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SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
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SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
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SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
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MVT::i64, MMO);
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SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
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array_lengthof(Ops), MVT::i64, MMO);
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APInt FF(32, 0x5F800000ULL);
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@ -8331,8 +8336,8 @@ X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOLoad, MemSize, MemSize);
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Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
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DstTy, MMO);
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Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
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array_lengthof(Ops), DstTy, MMO);
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Chain = Value.getValue(1);
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SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
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StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
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@ -8346,7 +8351,8 @@ X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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// Build the FP_TO_INT*_IN_MEM
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SDValue Ops[] = { Chain, Value, StackSlot };
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SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
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Ops, 3, DstTy, MMO);
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Ops, array_lengthof(Ops), DstTy,
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MMO);
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return std::make_pair(FIST, StackSlot);
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} else {
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SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
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@ -8358,8 +8364,8 @@ X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
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MVT::i32, eax.getValue(2));
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SDValue Ops[] = { eax, edx };
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SDValue pair = IsReplace
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? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
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: DAG.getMergeValues(Ops, 2, DL);
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? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
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: DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
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return std::make_pair(pair, SDValue());
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}
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}
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@ -10980,7 +10986,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
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SDValue(Result.getNode(), 1) };
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SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
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DAG.getVTList(Op->getValueType(1), MVT::Glue),
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Ops, 4);
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Ops, array_lengthof(Ops));
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// Return { result, isValid, chain }.
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return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
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@ -11278,7 +11284,8 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
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SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
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SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
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DAG.getVTList(MVT::Other),
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Ops, 2, MVT::i16, MMO);
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Ops, array_lengthof(Ops), MVT::i16,
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MMO);
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// Load FP Control Word from stack slot
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SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
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@ -12228,7 +12235,7 @@ static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
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SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
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Ops, 5, T, MMO);
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Ops, array_lengthof(Ops), T, MMO);
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SDValue cpOut =
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DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
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return cpOut;
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@ -12250,7 +12257,7 @@ static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
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DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
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rdx.getValue(1)
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};
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return DAG.getMergeValues(Ops, 2, dl);
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return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
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}
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SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
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@ -12514,7 +12521,7 @@ ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
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SDValue Ops[] = { Chain, In1, In2L, In2H };
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SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
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SDValue Result =
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DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
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DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
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cast<MemSDNode>(Node)->getMemOperand());
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SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
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Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
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@ -12594,7 +12601,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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eax.getValue(2));
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// Use a buildpair to merge the two 32-bit values into a 64-bit one.
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SDValue Ops[] = { eax, edx };
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Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
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Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
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array_lengthof(Ops)));
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Results.push_back(edx.getValue(1));
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return;
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}
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@ -12633,7 +12641,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
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X86ISD::LCMPXCHG8_DAG;
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SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
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Ops, 3, T, MMO);
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Ops, array_lengthof(Ops), T, MMO);
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SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
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Regs64bit ? X86::RAX : X86::EAX,
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HalfT, Result.getValue(1));
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@ -15120,7 +15128,8 @@ static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
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SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
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SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
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SDValue ResNode =
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DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
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DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
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array_lengthof(Ops),
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Ld->getMemoryVT(),
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Ld->getPointerInfo(),
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Ld->getAlignment(),
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