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[mips][mips64r6] Improve tests affected by the changes to multiplies and divides
Summary: MIPS32r6/MIPS64r6 support has not been added yet. inlineasm-cnstrnt-reg.ll: Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6 when -integrated-as is the default. We can't change the mnemonic since the LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no instructions that use LO. 2008-08-01-AsmInline.ll: Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit different code and this is a regression test. mips64instrs.ll and mips64muldiv.ll Check registers and the way the multiply is used in m1 divrem.ll Check registers and use multiple filecheck prefixes to limit redundancy Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida Reviewed By: matheusalmeida Subscribers: matheusalmeida Differential Revision: http://reviews.llvm.org/D3894 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210656 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
6b3f3922bf
commit
0ee5398b7f
@ -1,4 +1,4 @@
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; RUN: llc -march=mips < %s | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s
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%struct.DWstruct = type { i32, i32 }
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@ -1,77 +1,121 @@
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; RUN: llc -march=mips -verify-machineinstrs < %s |\
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; RUN: FileCheck %s -check-prefix=TRAP
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; RUN: llc -march=mips -mno-check-zero-division < %s |\
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; RUN: FileCheck %s -check-prefix=NOCHECK
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; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC -check-prefix=TRAP
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; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC -check-prefix=NOCHECK
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; TRAP-LABEL: sdiv1:
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; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; TRAP: teq $[[R0]], $zero, 7
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; TRAP: mflo
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; NOCHECK-LABEL: sdiv1:
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; NOCHECK-NOT: teq
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; NOCHECK: .end sdiv1
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; FileCheck Prefixes:
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; ALL - All targets
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; ACC - Accumulator based multiply/divide. I.e. All ISA's before MIPS32r6
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; TRAP - Division must be explicitly checked for divide by zero
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; NOCHECK - Division by zero will not be detected
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@g0 = common global i32 0, align 4
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@g1 = common global i32 0, align 4
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define i32 @sdiv1(i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: sdiv1:
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; ACC: div $zero, $4, $5
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; TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ACC: mflo $2
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; ALL: .end sdiv1
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%div = sdiv i32 %a0, %a1
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ret i32 %div
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}
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; TRAP-LABEL: srem1:
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; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; TRAP: teq $[[R0]], $zero, 7
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; TRAP: mfhi
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define i32 @srem1(i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: srem1:
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; ACC: div $zero, $4, $5
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; TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ACC: mfhi $2
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; ALL: .end srem1
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%rem = srem i32 %a0, %a1
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ret i32 %rem
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}
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; TRAP-LABEL: udiv1:
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; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; TRAP: teq $[[R0]], $zero, 7
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; TRAP: mflo
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define i32 @udiv1(i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: udiv1:
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; ACC: divu $zero, $4, $5
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; TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ACC: mflo $2
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; ALL: .end udiv1
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%div = udiv i32 %a0, %a1
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ret i32 %div
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}
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; TRAP-LABEL: urem1:
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; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; TRAP: teq $[[R0]], $zero, 7
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; TRAP: mfhi
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define i32 @urem1(i32 %a0, i32 %a1) nounwind readnone {
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entry:
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; ALL-LABEL: urem1:
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; ACC: divu $zero, $4, $5
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; TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ACC: mfhi $2
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; ALL: .end urem1
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%rem = urem i32 %a0, %a1
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ret i32 %rem
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}
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; TRAP: div $zero,
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define i32 @sdivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind {
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entry:
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; ALL-LABEL: sdivrem1:
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; ACC: div $zero, $4, $5
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; TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ACC: mflo $2
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; ACC: mfhi $[[R0:[0-9]+]]
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; ACC: sw $[[R0]], 0(${{[0-9]+}})
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; ALL: .end sdivrem1
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%rem = srem i32 %a0, %a1
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store i32 %rem, i32* %r, align 4
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%div = sdiv i32 %a0, %a1
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ret i32 %div
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}
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; TRAP: divu $zero,
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define i32 @udivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind {
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entry:
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; ALL-LABEL: udivrem1:
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; ACC: divu $zero, $4, $5
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; TRAP: teq $5, $zero, 7
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; NOCHECK-NOT: teq
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; ACC: mflo $2
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; ACC: mfhi $[[R0:[0-9]+]]
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; ACC: sw $[[R0]], 0(${{[0-9]+}})
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; ALL: .end udivrem1
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%rem = urem i32 %a0, %a1
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store i32 %rem, i32* %r, align 4
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%div = udiv i32 %a0, %a1
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ret i32 %div
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}
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; FIXME: It's not clear what this is supposed to test.
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define i32 @killFlags() {
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entry:
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%0 = load i32* @g0, align 4
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@ -1,6 +1,7 @@
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; Positive test for inline register constraints
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;
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; RUN: llc -march=mipsel < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
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define i32 @main() nounwind {
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entry:
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@ -1,99 +1,115 @@
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; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
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; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s
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@gll0 = common global i64 0, align 8
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@gll1 = common global i64 0, align 8
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define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: daddu
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; ALL-LABEL: f0:
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; ALL: daddu $2, ${{[45]}}, ${{[45]}}
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%add = add nsw i64 %a1, %a0
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ret i64 %add
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}
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define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dsubu
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; ALL-LABEL: f1:
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; ALL: dsubu $2, $4, $5
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%sub = sub nsw i64 %a0, %a1
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ret i64 %sub
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}
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define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: and
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; ALL-LABEL: f4:
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; ALL: and $2, ${{[45]}}, ${{[45]}}
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%and = and i64 %a1, %a0
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ret i64 %and
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}
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define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: or
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; ALL-LABEL: f5:
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; ALL: or $2, ${{[45]}}, ${{[45]}}
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%or = or i64 %a1, %a0
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ret i64 %or
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}
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define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: xor
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; ALL-LABEL: f6:
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; ALL: xor $2, ${{[45]}}, ${{[45]}}
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%xor = xor i64 %a1, %a0
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ret i64 %xor
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}
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define i64 @f7(i64 %a0) nounwind readnone {
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entry:
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; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20
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; ALL-LABEL: f7:
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; ALL: daddiu $2, $4, 20
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%add = add nsw i64 %a0, 20
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ret i64 %add
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}
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define i64 @f8(i64 %a0) nounwind readnone {
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entry:
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; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20
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; ALL-LABEL: f8:
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; ALL: daddiu $2, $4, -20
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%sub = add nsw i64 %a0, -20
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ret i64 %sub
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}
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define i64 @f9(i64 %a0) nounwind readnone {
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entry:
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; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20
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; ALL-LABEL: f9:
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; ALL: andi $2, $4, 20
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%and = and i64 %a0, 20
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ret i64 %and
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}
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define i64 @f10(i64 %a0) nounwind readnone {
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entry:
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; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20
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; ALL-LABEL: f10:
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; ALL: ori $2, $4, 20
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%or = or i64 %a0, 20
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ret i64 %or
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}
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define i64 @f11(i64 %a0) nounwind readnone {
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entry:
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; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20
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; ALL-LABEL: f11:
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; ALL: xori $2, $4, 20
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%xor = xor i64 %a0, 20
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ret i64 %xor
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}
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define i64 @f12(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: mult
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; ALL-LABEL: f12:
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; ALL: mult ${{[45]}}, ${{[45]}}
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%mul = mul nsw i64 %b, %a
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ret i64 %mul
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}
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define i64 @f13(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: mult
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; ALL-LABEL: f13:
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; ALL: mult ${{[45]}}, ${{[45]}}
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%mul = mul i64 %b, %a
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ret i64 %mul
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}
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define i64 @f14(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f14:
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; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mflo
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; ALL-LABEL: f14:
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; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
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; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
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; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
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; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
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; ALL: ddiv $zero, $[[T0]], $[[T1]]
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; ALL: teq $[[T1]], $zero, 7
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; ALL: mflo $2
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%0 = load i64* @gll0, align 8
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%1 = load i64* @gll1, align 8
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%div = sdiv i64 %0, %1
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@ -102,10 +118,14 @@ entry:
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define i64 @f15() nounwind readnone {
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entry:
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; CHECK-LABEL: f15:
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; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mflo
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; ALL-LABEL: f15:
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; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
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; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
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; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
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; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
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; ALL: ddivu $zero, $[[T0]], $[[T1]]
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; ALL: teq $[[T1]], $zero, 7
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; ALL: mflo $2
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%0 = load i64* @gll0, align 8
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%1 = load i64* @gll1, align 8
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%div = udiv i64 %0, %1
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@ -114,20 +134,20 @@ entry:
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define i64 @f16(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f16:
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; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mfhi
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; ALL-LABEL: f16:
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; ALL: ddiv $zero, $4, $5
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; ALL: teq $5, $zero, 7
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; ALL: mfhi $2
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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define i64 @f17(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f17:
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; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mfhi
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; ALL-LABEL: f17:
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; ALL: ddivu $zero, $4, $5
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; ALL: teq $5, $zero, 7
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; ALL: mfhi $2
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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@ -136,24 +156,24 @@ declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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define i64 @f18(i64 %X) nounwind readnone {
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entry:
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; CHECK-LABEL: f18:
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; ALL-LABEL: f18:
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; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
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; MIPS4-NOT: dclz
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; MIPS4-NOT: dclz
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; MIPS64: dclz $2, $4
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; MIPS64: dclz $2, $4
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
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ret i64 %tmp1
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}
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define i64 @f19(i64 %X) nounwind readnone {
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entry:
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; CHECK-LABEL: f19:
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; ALL-LABEL: f19:
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; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
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; MIPS4-NOT: dclo
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; MIPS4-NOT: dclo
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; MIPS64: dclo $2, $4
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; MIPS64: dclo $2, $4
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%neg = xor i64 %X, -1
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
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ret i64 %tmp1
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@ -161,8 +181,8 @@ entry:
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define i64 @f20(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f20:
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; CHECK: nor
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; ALL-LABEL: f20:
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; ALL: nor $2, ${{[45]}}, ${{[45]}}
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%or = or i64 %b, %a
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%neg = xor i64 %or, -1
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ret i64 %neg
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@ -1,50 +1,64 @@
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL
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define i64 @m0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dmult
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; CHECK: mflo
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; ALL-LABEL: m0:
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; ALL: dmult ${{[45]}}, ${{[45]}}
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; ALL: mflo $2
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%mul = mul i64 %a1, %a0
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ret i64 %mul
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}
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define i64 @m1(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: dmult
|
||||
; CHECK: mfhi
|
||||
; ALL-LABEL: m1:
|
||||
; ALL: lui $[[T0:[0-9]+]], 21845
|
||||
; ALL: addiu $[[T0]], $[[T0]], 21845
|
||||
; ALL: dsll $[[T0]], $[[T0]], 16
|
||||
; ALL: addiu $[[T0]], $[[T0]], 21845
|
||||
; ALL: dsll $[[T0]], $[[T0]], 16
|
||||
; ALL: addiu $[[T0]], $[[T0]], 21846
|
||||
; ALL: dmult ${{[45]}}, $[[T0]]
|
||||
; ALL: mfhi $[[T1:[0-9]+]]
|
||||
; ALL: dsrl $2, $[[T1]], 63
|
||||
; ALL: daddu $2, $[[T1]], $2
|
||||
%div = sdiv i64 %a, 3
|
||||
ret i64 %div
|
||||
}
|
||||
|
||||
define i64 @d0(i64 %a0, i64 %a1) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: ddivu
|
||||
; CHECK: mflo
|
||||
; ALL-LABEL: d0:
|
||||
; ALL: ddivu $zero, $4, $5
|
||||
; ALL: mflo $2
|
||||
%div = udiv i64 %a0, %a1
|
||||
ret i64 %div
|
||||
}
|
||||
|
||||
define i64 @d1(i64 %a0, i64 %a1) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: ddiv
|
||||
; CHECK: mflo
|
||||
; ALL-LABEL: d1:
|
||||
; ALL: ddiv $zero, $4, $5
|
||||
; ALL: mflo $2
|
||||
%div = sdiv i64 %a0, %a1
|
||||
ret i64 %div
|
||||
}
|
||||
|
||||
define i64 @d2(i64 %a0, i64 %a1) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: ddivu
|
||||
; CHECK: mfhi
|
||||
; ALL-LABEL: d2:
|
||||
; ALL: ddivu $zero, $4, $5
|
||||
; ALL: mfhi $2
|
||||
%rem = urem i64 %a0, %a1
|
||||
ret i64 %rem
|
||||
}
|
||||
|
||||
define i64 @d3(i64 %a0, i64 %a1) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: ddiv
|
||||
; CHECK: mfhi
|
||||
; ALL-LABEL: d3:
|
||||
; ALL: ddiv $zero, $4, $5
|
||||
; ALL: mfhi $2
|
||||
%rem = srem i64 %a0, %a1
|
||||
ret i64 %rem
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user