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crc32 with 64-bit output zeros upper 32-bits. rdar://9467055

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131664 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-05-19 18:57:12 +00:00
parent 3dfc4b1222
commit 0efaa5e6a1
2 changed files with 32 additions and 0 deletions
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13
lib/Target/X86/X86ISelLowering.cpp
View File

@ -10939,6 +10939,19 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
Mask.getBitWidth() - 1);
break;
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) {
default: break;
case Intrinsic::x86_sse42_crc64_8:
case Intrinsic::x86_sse42_crc64_64:
// crc32 with 64-bit destination zeros high 32-bit.
KnownZero |= APInt::getHighBitsSet(64, 32);
break;
}
break;
}
}
}

19
test/CodeGen/X86/crc64.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llc < %s -march=x86-64 -mattr=sse42 | FileCheck %s
; crc32 with 64-bit destination zeros high 32-bit.
; rdar://9467055
define i64 @t() nounwind {
entry:
; CHECK: t:
; CHECK: crc32q
; CHECK-NOT: mov
; CHECK-NEXT: crc32q
%0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
%1 = and i64 %0, 4294967295
%2 = tail call i64 @llvm.x86.sse42.crc64.64(i64 %1, i64 4) nounwind
%3 = and i64 %2, 4294967295
ret i64 %3
}
declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone