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- Add "Bitcast" target instruction property for instructions which perform
nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -200,6 +200,7 @@ class Instruction {
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bit isIndirectBranch = 0; // Is this instruction an indirect branch?
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bit isIndirectBranch = 0; // Is this instruction an indirect branch?
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bit isCompare = 0; // Is this instruction a comparison instruction?
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bit isCompare = 0; // Is this instruction a comparison instruction?
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bit isMoveImm = 0; // Is this instruction a move immediate instruction?
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bit isMoveImm = 0; // Is this instruction a move immediate instruction?
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bit isBitcast = 0; // Is this instruction a bitcast instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
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bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
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@ -105,6 +105,7 @@ namespace TID {
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IndirectBranch,
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IndirectBranch,
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Compare,
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Compare,
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MoveImm,
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MoveImm,
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Bitcast,
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DelaySlot,
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DelaySlot,
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FoldableAsLoad,
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FoldableAsLoad,
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MayLoad,
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MayLoad,
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@ -358,6 +359,12 @@ public:
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bool isMoveImmediate() const {
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bool isMoveImmediate() const {
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return Flags & (1 << TID::MoveImm);
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return Flags & (1 << TID::MoveImm);
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}
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}
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/// isBitcast - Return true if this instruction is a bitcast instruction.
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///
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bool isBitcast() const {
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return Flags & (1 << TID::Bitcast);
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}
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// isNotDuplicable - Return true if this instruction cannot be safely
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/// duplicated. For example, if the instruction has a unique labels attached
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/// duplicated. For example, if the instruction has a unique labels attached
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@ -2288,13 +2288,14 @@ class InstAnalyzer {
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const CodeGenDAGPatterns &CDP;
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const CodeGenDAGPatterns &CDP;
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bool &mayStore;
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bool &mayStore;
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bool &mayLoad;
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bool &mayLoad;
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bool &IsBitcast;
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bool &HasSideEffects;
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bool &HasSideEffects;
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bool &IsVariadic;
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bool &IsVariadic;
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public:
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public:
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InstAnalyzer(const CodeGenDAGPatterns &cdp,
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InstAnalyzer(const CodeGenDAGPatterns &cdp,
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bool &maystore, bool &mayload, bool &hse, bool &isv)
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bool &maystore, bool &mayload, bool &isbc, bool &hse, bool &isv)
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: CDP(cdp), mayStore(maystore), mayLoad(mayload), HasSideEffects(hse),
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: CDP(cdp), mayStore(maystore), mayLoad(mayload), IsBitcast(isbc),
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IsVariadic(isv) {
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HasSideEffects(hse), IsVariadic(isv) {
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}
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}
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/// Analyze - Analyze the specified instruction, returning true if the
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/// Analyze - Analyze the specified instruction, returning true if the
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@ -2313,6 +2314,29 @@ public:
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}
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}
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private:
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private:
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bool IsNodeBitcast(const TreePatternNode *N) const {
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if (HasSideEffects || mayLoad || mayStore || IsVariadic)
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return false;
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if (N->getNumChildren() != 2)
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return false;
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const TreePatternNode *N0 = N->getChild(0);
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if (!N0->isLeaf() || !dynamic_cast<DefInit*>(N0->getLeafValue()))
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return false;
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const TreePatternNode *N1 = N->getChild(1);
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if (N1->isLeaf())
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return false;
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if (N1->getNumChildren() != 1 || !N1->getChild(0)->isLeaf())
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return false;
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const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N1->getOperator());
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if (OpInfo.getNumResults() != 1 || OpInfo.getNumOperands() != 1)
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return false;
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return OpInfo.getEnumName() == "ISD::BITCAST";
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}
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void AnalyzeNode(const TreePatternNode *N) {
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void AnalyzeNode(const TreePatternNode *N) {
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if (N->isLeaf()) {
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if (N->isLeaf()) {
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if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
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if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
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@ -2333,8 +2357,10 @@ private:
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AnalyzeNode(N->getChild(i));
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AnalyzeNode(N->getChild(i));
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// Ignore set nodes, which are not SDNodes.
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// Ignore set nodes, which are not SDNodes.
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if (N->getOperator()->getName() == "set")
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if (N->getOperator()->getName() == "set") {
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IsBitcast = IsNodeBitcast(N);
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return;
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return;
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}
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// Get information about the SDNode for the operator.
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// Get information about the SDNode for the operator.
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const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
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const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator());
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@ -2363,12 +2389,13 @@ private:
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static void InferFromPattern(const CodeGenInstruction &Inst,
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static void InferFromPattern(const CodeGenInstruction &Inst,
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bool &MayStore, bool &MayLoad,
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bool &MayStore, bool &MayLoad,
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bool &IsBitcast,
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bool &HasSideEffects, bool &IsVariadic,
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bool &HasSideEffects, bool &IsVariadic,
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const CodeGenDAGPatterns &CDP) {
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const CodeGenDAGPatterns &CDP) {
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MayStore = MayLoad = HasSideEffects = IsVariadic = false;
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MayStore = MayLoad = IsBitcast = HasSideEffects = IsVariadic = false;
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bool HadPattern =
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bool HadPattern =
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InstAnalyzer(CDP, MayStore, MayLoad, HasSideEffects, IsVariadic)
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InstAnalyzer(CDP, MayStore, MayLoad, IsBitcast, HasSideEffects, IsVariadic)
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.Analyze(Inst.TheDef);
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.Analyze(Inst.TheDef);
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// InstAnalyzer only correctly analyzes mayStore/mayLoad so far.
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// InstAnalyzer only correctly analyzes mayStore/mayLoad so far.
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@ -2714,11 +2741,12 @@ void CodeGenDAGPatterns::InferInstructionFlags() {
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CodeGenInstruction &InstInfo =
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CodeGenInstruction &InstInfo =
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const_cast<CodeGenInstruction &>(*Instructions[i]);
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const_cast<CodeGenInstruction &>(*Instructions[i]);
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// Determine properties of the instruction from its pattern.
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// Determine properties of the instruction from its pattern.
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bool MayStore, MayLoad, HasSideEffects, IsVariadic;
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bool MayStore, MayLoad, IsBitcast, HasSideEffects, IsVariadic;
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InferFromPattern(InstInfo, MayStore, MayLoad, HasSideEffects, IsVariadic,
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InferFromPattern(InstInfo, MayStore, MayLoad, IsBitcast,
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*this);
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HasSideEffects, IsVariadic, *this);
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InstInfo.mayStore = MayStore;
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InstInfo.mayStore = MayStore;
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InstInfo.mayLoad = MayLoad;
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InstInfo.mayLoad = MayLoad;
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InstInfo.isBitcast = IsBitcast;
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InstInfo.hasSideEffects = HasSideEffects;
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InstInfo.hasSideEffects = HasSideEffects;
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InstInfo.Operands.isVariadic = IsVariadic;
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InstInfo.Operands.isVariadic = IsVariadic;
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}
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}
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@ -288,6 +288,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) {
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isIndirectBranch = R->getValueAsBit("isIndirectBranch");
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isIndirectBranch = R->getValueAsBit("isIndirectBranch");
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isCompare = R->getValueAsBit("isCompare");
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isCompare = R->getValueAsBit("isCompare");
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isMoveImm = R->getValueAsBit("isMoveImm");
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isMoveImm = R->getValueAsBit("isMoveImm");
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isBitcast = R->getValueAsBit("isBitcast");
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isBarrier = R->getValueAsBit("isBarrier");
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isBarrier = R->getValueAsBit("isBarrier");
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isCall = R->getValueAsBit("isCall");
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isCall = R->getValueAsBit("isCall");
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canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
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canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
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@ -215,6 +215,7 @@ namespace llvm {
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bool isIndirectBranch;
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bool isIndirectBranch;
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bool isCompare;
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bool isCompare;
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bool isMoveImm;
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bool isMoveImm;
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bool isBitcast;
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bool isBarrier;
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bool isBarrier;
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bool isCall;
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bool isCall;
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bool canFoldAsLoad;
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bool canFoldAsLoad;
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@ -272,6 +272,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
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if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
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if (Inst.isCompare) OS << "|(1<<TID::Compare)";
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if (Inst.isCompare) OS << "|(1<<TID::Compare)";
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if (Inst.isMoveImm) OS << "|(1<<TID::MoveImm)";
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if (Inst.isMoveImm) OS << "|(1<<TID::MoveImm)";
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if (Inst.isBitcast) OS << "|(1<<TID::Bitcast)";
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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