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Adjust to changes in getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26306 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1198,13 +1198,6 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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SDOperand Chain = getRoot();
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SDOperand Flag;
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// Loop over all of the inputs, copying the operand values into the
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// appropriate registers and processing the output regs.
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unsigned RetValReg = 0;
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std::vector<std::pair<unsigned, Value*> > IndirectStoresToEmit;
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unsigned OpNum = 1;
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bool FoundOutputConstraint = false;
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// We fully assign registers here at isel time. This is not optimal, but
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// should work. For register classes that correspond to LLVM classes, we
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// could let the LLVM RA do its thing, but we currently don't. Do a prepass
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@ -1215,7 +1208,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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std::string &ConstraintCode = Constraints[i].Codes[0];
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std::vector<unsigned> Regs =
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TLI.getRegForInlineAsmConstraint(ConstraintCode);
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TLI.getRegForInlineAsmConstraint(ConstraintCode, MVT::Other);
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if (Regs.size() != 1) continue; // Not assigned a fixed reg.
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unsigned TheReg = Regs[0];
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@ -1240,14 +1233,23 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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}
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}
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// Loop over all of the inputs, copying the operand values into the
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// appropriate registers and processing the output regs.
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unsigned RetValReg = 0;
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std::vector<std::pair<unsigned, Value*> > IndirectStoresToEmit;
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bool FoundOutputConstraint = false;
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unsigned OpNum = 1;
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for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
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assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
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std::string &ConstraintCode = Constraints[i].Codes[0];
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Value *CallOperand = I.getOperand(OpNum);
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MVT::ValueType CallOpVT = TLI.getValueType(CallOperand->getType());
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switch (Constraints[i].Type) {
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case InlineAsm::isOutput: {
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// Copy the output from the appropriate register.
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std::vector<unsigned> Regs =
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TLI.getRegForInlineAsmConstraint(ConstraintCode);
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TLI.getRegForInlineAsmConstraint(ConstraintCode, CallOpVT);
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// Find a regsister that we can use.
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unsigned DestReg;
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@ -1276,9 +1278,8 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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RetValReg = DestReg;
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OpTy = I.getType();
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} else {
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IndirectStoresToEmit.push_back(std::make_pair(DestReg,
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I.getOperand(OpNum)));
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OpTy = I.getOperand(OpNum)->getType();
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IndirectStoresToEmit.push_back(std::make_pair(DestReg, CallOperand));
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OpTy = CallOperand->getType();
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OpTy = cast<PointerType>(OpTy)->getElementType();
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OpNum++; // Consumes a call operand.
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}
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@ -1292,21 +1293,20 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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break;
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}
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case InlineAsm::isInput: {
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Value *Operand = I.getOperand(OpNum);
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const Type *OpTy = Operand->getType();
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const Type *OpTy = CallOperand->getType();
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OpNum++; // Consumes a call operand.
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unsigned SrcReg;
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SDOperand ResOp;
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unsigned ResOpType;
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SDOperand InOperandVal = getValue(Operand);
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SDOperand InOperandVal = getValue(CallOperand);
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if (isdigit(ConstraintCode[0])) { // Matching constraint?
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// If this is required to match an output register we have already set,
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// just use its register.
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unsigned OperandNo = atoi(ConstraintCode.c_str());
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SrcReg = cast<RegisterSDNode>(AsmNodeOperands[OperandNo*2+2])->getReg();
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ResOp = DAG.getRegister(SrcReg, TLI.getValueType(OpTy));
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ResOp = DAG.getRegister(SrcReg, CallOpVT);
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ResOpType = 1;
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Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
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@ -1321,7 +1321,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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case TargetLowering::C_RegisterClass: {
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// Copy the input into the appropriate register.
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std::vector<unsigned> Regs =
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TLI.getRegForInlineAsmConstraint(ConstraintCode);
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TLI.getRegForInlineAsmConstraint(ConstraintCode, CallOpVT);
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if (Regs.size() == 1)
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SrcReg = Regs[0];
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else
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@ -1332,7 +1332,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
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Flag = Chain.getValue(1);
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ResOp = DAG.getRegister(SrcReg, TLI.getValueType(OpTy));
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ResOp = DAG.getRegister(SrcReg, CallOpVT);
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ResOpType = 1;
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break;
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}
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