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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Make LowerVSETCC aware of AVX types and add patterns to match them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137090 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -989,6 +989,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SRA, MVT::v8i32, Custom);
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setOperationAction(ISD::SRA, MVT::v8i32, Custom);
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setOperationAction(ISD::SRA, MVT::v16i16, Custom);
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setOperationAction(ISD::SRA, MVT::v16i16, Custom);
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setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
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setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
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// Custom lower several nodes for 256-bit types.
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// Custom lower several nodes for 256-bit types.
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
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@ -7912,9 +7915,10 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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if (isFP) {
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if (isFP) {
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unsigned SSECC = 8;
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unsigned SSECC = 8;
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EVT VT0 = Op0.getValueType();
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EVT EltVT = Op0.getValueType().getVectorElementType();
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assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
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assert(EltVT == MVT::f32 || EltVT == MVT::f64);
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unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
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unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
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bool Swap = false;
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bool Swap = false;
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switch (SetCCOpcode) {
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switch (SetCCOpcode) {
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@ -7961,6 +7965,9 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
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return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
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}
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}
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if (!isFP && VT.getSizeInBits() == 256)
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return SDValue();
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// We are handling one of the integer comparisons here. Since SSE only has
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// We are handling one of the integer comparisons here. Since SSE only has
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// GT and EQ comparisons for integer, swapping operands and multiple
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// GT and EQ comparisons for integer, swapping operands and multiple
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// operations may be required for some comparisons.
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// operations may be required for some comparisons.
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@ -1264,14 +1264,39 @@ let Constraints = "$src1 = $dst" in {
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SSEPackedDouble>, TB, OpSize;
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SSEPackedDouble>, TB, OpSize;
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}
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}
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let Predicates = [HasSSE1] in {
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
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(CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
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(CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
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(CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
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}
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let Predicates = [HasSSE2] in {
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
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(CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
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(CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
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(CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
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}
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let Predicates = [HasAVX] in {
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
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(VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
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(VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
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def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
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(VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
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def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
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(VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
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def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
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(VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
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def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
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(VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Shuffle Instructions
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// SSE 1 & 2 - Shuffle Instructions
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18
test/CodeGen/X86/avx-256-cmp.ll
Normal file
18
test/CodeGen/X86/avx-256-cmp.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: vcmpltps %ymm
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; CHECK-NOT: vucomiss
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define <8 x i32> @cmp00(<8 x float> %a, <8 x float> %b) nounwind readnone {
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%bincmp = fcmp olt <8 x float> %a, %b
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%s = sext <8 x i1> %bincmp to <8 x i32>
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ret <8 x i32> %s
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}
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; CHECK: vcmpltpd %ymm
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; CHECK-NOT: vucomisd
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define <4 x i64> @cmp01(<4 x double> %a, <4 x double> %b) nounwind readnone {
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%bincmp = fcmp olt <4 x double> %a, %b
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%s = sext <4 x i1> %bincmp to <4 x i64>
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ret <4 x i64> %s
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}
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