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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-07 12:28:24 +00:00
Fix order of operands for crc8_l4r
The order in which operands appear in the encoded instruction is different to order in which they appear in assembly. This changes the XCore backend to use the instruction encoding order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173493 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -211,16 +211,11 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
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return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
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Ops, 4);
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
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switch (IntNo) {
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case Intrinsic::xcore_crc8:
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SDValue Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3) };
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case XCoreISD::CRC8: {
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SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) };
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return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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break;
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}
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case ISD::BRIND:
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if (SDNode *ResNode = SelectBRIND(N))
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return ResNode;
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@@ -54,6 +54,7 @@ getTargetNodeName(unsigned Opcode) const
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case XCoreISD::LMUL : return "XCoreISD::LMUL";
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case XCoreISD::MACCU : return "XCoreISD::MACCU";
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case XCoreISD::MACCS : return "XCoreISD::MACCS";
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case XCoreISD::CRC8 : return "XCoreISD::CRC8";
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case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
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case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
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default : return NULL;
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@@ -152,6 +153,9 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
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setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
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setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
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// We want to custom lower some of our intrinsics.
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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maxStoresPerMemset = maxStoresPerMemsetOptSize = 4;
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maxStoresPerMemmove = maxStoresPerMemmoveOptSize
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= maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2;
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@@ -185,6 +189,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
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case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
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case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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default:
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llvm_unreachable("unimplemented operand");
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}
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@@ -858,6 +863,23 @@ LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5);
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}
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SDValue XCoreTargetLowering::
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LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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switch (IntNo) {
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case Intrinsic::xcore_crc8:
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EVT VT = Op.getValueType();
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SDValue Data =
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DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
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Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
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SDValue Crc(Data.getNode(), 1);
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SDValue Results[] = { Crc, Data };
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return DAG.getMergeValues(Results, 2, DL);
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}
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return SDValue();
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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@@ -63,6 +63,9 @@ namespace llvm {
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// Corresponds to MACCS instruction
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MACCS,
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// Corresponds to CRC8 instruction
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CRC8,
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// Jumptable branch.
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BR_JT,
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@@ -147,6 +150,7 @@ namespace llvm {
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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// Inline asm support
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std::pair<unsigned, const TargetRegisterClass*>
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@@ -477,10 +477,10 @@ def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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[]>;
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}
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let Constraints = "$src1 = $dst1" in
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let Constraints = "$src1 = $dst2" in
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def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"crc8 $dst1, $dst2, $src2, $src3",
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"crc8 $dst2, $dst1, $src2, $src3",
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[]>;
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// Five operand long
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