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Fix a regression in the 32-bit port from the 64-bit port landing.
We now compile CodeGen/X86/lea-2.ll into: _test: movl 4(%esp), %eax movl 8(%esp), %ecx leal -5(%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal (,%eax,4), %eax addl 8(%esp), %eax addl $4294967291, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30288 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -498,7 +498,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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// RIP relative addressing: %rip + 32-bit displacement!
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if (AM.isRIPRel) {
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if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
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uint64_t Val = cast<ConstantSDNode>(N)->getValue();
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int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
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if (isInt32(AM.Disp + Val)) {
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AM.Disp += Val;
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return false;
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@ -513,7 +513,7 @@ bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant: {
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uint64_t Val = cast<ConstantSDNode>(N)->getValue();
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int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
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if (isInt32(AM.Disp + Val)) {
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AM.Disp += Val;
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return false;
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