6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

Add lswi / stswi for assembler use with a warning to not add patterns

Browse Source 
for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joerg Sonnenberger 2014-08-05 13:34:01 +00:00
parent 68b3d680f2
commit 0f365741f3
3 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -3037,6 +3037,16 @@ def : Pat<(i1 (not (trunc i64:$in))),
// PowerPC Instructions used for assembler/disassembler only
//
// FIXME: For B=0 or B > 8, the registers following RT are used.
// WARNING: Do not add patterns for this instruction without fixing this.
def LSWI : XForm_base_r3xo<31, 597, (outs gprc:$RT), (ins gprc:$A, u5imm:$B),
"lswi $RT, $A, $B", IIC_LdStLoad, []>;
// FIXME: For B=0 or B > 8, the registers following RT are used.
// WARNING: Do not add patterns for this instruction without fixing this.
def STSWI : XForm_base_r3xo<31, 725, (outs), (ins gprc:$RT, gprc:$A, u5imm:$B),
"stswi $RT, $A, $B", IIC_LdStLoad, []>;
def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
"isync", IIC_SprISYNC, []>;

5
test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt
View File

@ -2266,3 +2266,8 @@
# CHECK: tlbia
0x7c 0x00 0x02 0xe4
# CHECK: lswi 8, 6, 7
0x7d 0x06 0x3c 0xaa
# CHECK: stswi 8, 6, 7
0x7d 0x06 0x3d 0xaa

7
test/MC/PowerPC/ppc64-encoding-ext.s
View File

@ -3609,3 +3609,10 @@
# CHECK-BE: tlbia # encoding: [0x7c,0x00,0x02,0xe4]
# CHECK-LE: tlbia # encoding: [0xe4,0x02,0x00,0x7c]
tlbia
# CHECK-BE: lswi 8, 6, 7 # encoding: [0x7d,0x06,0x3c,0xaa]
# CHECK-LE: lswi 8, 6, 7 # encoding: [0xaa,0x3c,0x06,0x7d]
lswi %r8, %r6, 7
# CHECK-BE: stswi 8, 6, 7 # encoding: [0x7d,0x06,0x3d,0xaa]
# CHECK-LE: stswi 8, 6, 7 # encoding: [0xaa,0x3d,0x06,0x7d]
stswi %r8, %r6, 7