mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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0cfd73a9c1
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@ -40,9 +40,6 @@ def ARMInstrInfo : InstrInfo {
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//===----------------------------------------------------------------------===//
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def ARM : Target {
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// FIXME: Specify callee-saved registers
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let CalleeSavedRegisters = [];
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// Pull in Instruction Info:
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let InstructionSet = ARMInstrInfo;
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}
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@ -58,6 +58,17 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
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return NULL;
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}
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const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = { 0 };
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const *
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ARMRegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
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return CalleeSaveRegClasses;
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}
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void ARMRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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@ -45,6 +45,10 @@ struct ARMRegisterInfo : public ARMGenRegisterInfo {
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unsigned OpNum,
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int FrameIndex) const;
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const unsigned *getCalleeSaveRegs() const;
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const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -65,17 +65,6 @@ def : Processor<"ev67" , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
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def Alpha : Target {
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let CalleeSavedRegisters =
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//saved regs
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[R9, R10, R11, R12, R13, R14,
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//Frame pointer
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// R15,
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//return address
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// R26,
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//Stack Pointer
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// R30,
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F2, F3, F4, F5, F6, F7, F8, F9];
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// Pull in Instruction Info:
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let InstructionSet = AlphaInstrInfo;
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}
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@ -145,6 +145,33 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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}
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}
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const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = {
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Alpha::R9, Alpha::R10,
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Alpha::R11, Alpha::R12,
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Alpha::R13, Alpha::R14,
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Alpha::F2, Alpha::F3,
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Alpha::F4, Alpha::F5,
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Alpha::F6, Alpha::F7,
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Alpha::F8, Alpha::F9, 0
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};
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const*
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AlphaRegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
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&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
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&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
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&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
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&Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
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};
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return CalleeSaveRegClasses;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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@ -42,6 +42,10 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const;
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const unsigned *getCalleeSaveRegs() const;
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const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -31,66 +31,6 @@ include "IA64InstrInfo.td"
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def IA64InstrInfo : InstrInfo { }
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def IA64 : Target {
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// The following registers are always saved across calls:
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let CalleeSavedRegisters =
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//'preserved' GRs:
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[
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r5 // the 'frame pointer' (base pointer) reg
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// We never generate references to these regs, so we don't need to declare
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// that they are saved. In fact, we could just remove them entirely.
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//r4, r6, r7,
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//'special' GRs:
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// r1, // global data pointer (GP) - XXX NOT callee saved, we do it ourselves
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// r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves
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// rp, // return branch register (rp/b0) - we do this ourselves
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// **** r13 (thread pointer) we do not touch, ever. it's not here. ****//
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//'stacked' GRs the RSE takes care of, we don't worry about
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/* We don't want PEI::calculateCallerSavedRegisters to worry about them,
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since the RSE takes care of them (and we determinethe appropriate
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'alloc' instructions and save/restore ar.pfs ourselves, in instruction
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selection)
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**************************************************************************
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* r32, r33, r34, r35,
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* r36, r37, r38, r39, r40, r41, r42, r43, r44, r45, r46, r47,
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* r48, r49, r50, r51, r52, r53, r54, r55, r56, r57, r58, r59,
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* r60, r61, r62, r63, r64, r65, r66, r67, r68, r69, r70, r71,
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* r72, r73, r74, r75, r76, r77, r78, r79, r80, r81, r82, r83,
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* r84, r85, r86, r87, r88, r89, r90, r91, r92, r93, r94, r95,
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* r96, r97, r98, r99, r100, r101, r102, r103, r104, r105, r106, r107,
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* r108, r109, r110, r111, r112, r113, r114, r115, r116, r117, r118, r119,
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* r120, r121, r122, r123, r124, r125, r126, r127,
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**************************************************************************
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*/
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//'preserved' FP regs:
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/* We never generate references to these regs, so we don't need to declare
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* that they are saved. In fact, we could just remove them entirely.
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* F2,F3,F4, F5,
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* F16,F17,F18,F19,F20,F21,F22,F23,
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* F24,F25,F26,F27,F28,F29,F30,F31,
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*/
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//'preserved' predicate regs:
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/* We never generate references to these regs, so we don't need to declare
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that they are saved. In fact, we could just remove them entirely.
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p1, p2, p3, p4, p5,
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p16, p17, p18, p19, p20, p21, p22, p23,
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p24, p25, p26, p27, p28, p29, p30, p31,
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p32, p33, p34, p35, p36, p37, p38, p39,
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p40, p41, p42, p43, p44, p45, p46, p47,
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p48, p49, p50, p51, p52, p53, p54, p55,
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p56, p57, p58, p59, p60, p61, p62, p63
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*/
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];
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// Our instruction set
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let InstructionSet = IA64InstrInfo;
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@ -90,6 +90,21 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
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}
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const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = {
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IA64::r5, 0
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};
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const*
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IA64RegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
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&IA64::GRRegClass, 0
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};
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return CalleeSaveRegClasses;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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@ -40,6 +40,10 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const;
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const unsigned *getCalleeSaveRegs() const;
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const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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@ -83,13 +83,4 @@ def PPCInstrInfo : InstrInfo {
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def PPC : Target {
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// Information about the instructions.
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let InstructionSet = PPCInstrInfo;
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// According to the Mach-O Runtime ABI, these regs are nonvolatile across
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// calls
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let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
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F30, F31, CR2, CR3, CR4, V20, V21, V22, V23, V24, V25, V26, V27, V28,
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V29, V30, V31, LR];
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}
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@ -182,6 +182,73 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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}
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}
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const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = {
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PPC::R1, PPC::R13,
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PPC::R14, PPC::R15,
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PPC::R16, PPC::R17,
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PPC::R18, PPC::R19,
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PPC::R20, PPC::R21,
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PPC::R22, PPC::R23,
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PPC::R24, PPC::R25,
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PPC::R26, PPC::R27,
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PPC::R28, PPC::R29,
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PPC::R30, PPC::R31,
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PPC::F14, PPC::F15,
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PPC::F16, PPC::F17,
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PPC::F18, PPC::F19,
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PPC::F20, PPC::F21,
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PPC::F22, PPC::F23,
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PPC::F24, PPC::F25,
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PPC::F26, PPC::F27,
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PPC::F28, PPC::F29,
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PPC::F30, PPC::F31,
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PPC::CR2, PPC::CR3,
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PPC::CR4, PPC::V20,
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PPC::V21, PPC::V22,
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PPC::V23, PPC::V24,
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PPC::V25, PPC::V26,
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PPC::V27, PPC::V28,
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PPC::V29, PPC::V30,
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PPC::V31, PPC::LR, 0
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};
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const*
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PPCRegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::GPRCRegClass, &PPC::GPRCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::F8RCRegClass, &PPC::F8RCRegClass,
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&PPC::CRRCRegClass, &PPC::CRRCRegClass,
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&PPC::CRRCRegClass, &PPC::VRRCRegClass,
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&PPC::VRRCRegClass, &PPC::VRRCRegClass,
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&PPC::VRRCRegClass, &PPC::VRRCRegClass,
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&PPC::VRRCRegClass, &PPC::VRRCRegClass,
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&PPC::VRRCRegClass, &PPC::VRRCRegClass,
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&PPC::VRRCRegClass, &PPC::VRRCRegClass,
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&PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
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};
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return CalleeSaveRegClasses;
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}
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/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
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/// copy instructions, turning them into load/store instructions.
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MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
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@ -51,6 +51,10 @@ public:
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
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int FrameIndex) const;
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const unsigned *getCalleeSaveRegs() const;
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const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -75,9 +75,6 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
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//===----------------------------------------------------------------------===//
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def Sparc : Target {
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// FIXME: Specify callee-saved registers
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let CalleeSavedRegisters = [];
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// Pull in Instruction Info:
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let InstructionSet = SparcInstrInfo;
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}
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@ -103,6 +103,18 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
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return 0;
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}
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const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = { 0 };
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const*
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SparcRegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
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return CalleeSaveRegClasses;
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}
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void SparcRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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@ -46,6 +46,10 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
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unsigned OpNum,
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int FrameIndex) const;
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const unsigned *getCalleeSaveRegs() const;
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const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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@ -130,9 +130,6 @@ def IntelAsmWriter : AsmWriter {
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def X86 : Target {
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// Specify the callee saved registers.
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let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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@ -600,6 +600,22 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
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return NULL;
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}
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const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = {
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X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
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};
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const*
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X86RegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
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&X86::GR32RegClass, &X86::GR32RegClass,
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&X86::GR32RegClass, &X86::GR32RegClass, 0
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};
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return CalleeSaveRegClasses;
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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@ -47,10 +47,18 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
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/// folding and return true, otherwise it should return false. If it folds
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/// the instruction, it is likely that the MachineInstruction the iterator
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/// references has been changed.
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virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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int FrameIndex) const;
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MachineInstr* foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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int FrameIndex) const;
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/// getCalleeSaveRegs - Return a null-terminated list of all of the
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/// callee-save registers on this target.
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const unsigned *getCalleeSaveRegs() const;
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/// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
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/// register classes to spill each callee-saved register with. The order and
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/// length of this list match the getCalleeSaveRegs() list.
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const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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