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R600: Switch to using generic min / max nodes.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239377 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2015-06-09 00:52:37 +00:00
parent d99ce2f630
commit 0f59d850fa
6 changed files with 39 additions and 56 deletions
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37
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -314,6 +314,11 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
setOperationAction(ISD::SMIN, MVT::i32, Legal);
setOperationAction(ISD::UMIN, MVT::i32, Legal);
setOperationAction(ISD::SMAX, MVT::i32, Legal);
setOperationAction(ISD::UMAX, MVT::i32, Legal);
if (!Subtarget->hasFFBH()) if (!Subtarget->hasFFBH())
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
@ -975,16 +980,16 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
Op.getOperand(2)); Op.getOperand(2));
case AMDGPUIntrinsic::AMDGPU_imax: case AMDGPUIntrinsic::AMDGPU_imax:
return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
Op.getOperand(2)); Op.getOperand(2));
case AMDGPUIntrinsic::AMDGPU_umax: case AMDGPUIntrinsic::AMDGPU_umax:
return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
Op.getOperand(2)); Op.getOperand(2));
case AMDGPUIntrinsic::AMDGPU_imin: case AMDGPUIntrinsic::AMDGPU_imin:
return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1), return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
Op.getOperand(2)); Op.getOperand(2));
case AMDGPUIntrinsic::AMDGPU_umin: case AMDGPUIntrinsic::AMDGPU_umin:
return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1), return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
Op.getOperand(2)); Op.getOperand(2));
case AMDGPUIntrinsic::AMDGPU_umul24: case AMDGPUIntrinsic::AMDGPU_umul24:
@ -1063,7 +1068,7 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
Op.getOperand(1)); Op.getOperand(1));
return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1)); return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
} }
/// Linear Interpolation /// Linear Interpolation
@ -1162,7 +1167,7 @@ SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
return SDValue(); return SDValue();
} }
/// \brief Generate Min/Max node // FIXME: Remove this when combines added to DAGCombiner.
SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL, SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
EVT VT, EVT VT,
SDValue LHS, SDValue LHS,
@ -1178,22 +1183,22 @@ SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
switch (CCOpcode) { switch (CCOpcode) {
case ISD::SETULE: case ISD::SETULE:
case ISD::SETULT: { case ISD::SETULT: {
unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX; unsigned Opc = (LHS == True) ? ISD::UMIN : ISD::UMAX;
return DAG.getNode(Opc, DL, VT, LHS, RHS); return DAG.getNode(Opc, DL, VT, LHS, RHS);
} }
case ISD::SETLE: case ISD::SETLE:
case ISD::SETLT: { case ISD::SETLT: {
unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX; unsigned Opc = (LHS == True) ? ISD::SMIN : ISD::SMAX;
return DAG.getNode(Opc, DL, VT, LHS, RHS); return DAG.getNode(Opc, DL, VT, LHS, RHS);
} }
case ISD::SETGT: case ISD::SETGT:
case ISD::SETGE: { case ISD::SETGE: {
unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN; unsigned Opc = (LHS == True) ? ISD::SMAX : ISD::SMIN;
return DAG.getNode(Opc, DL, VT, LHS, RHS); return DAG.getNode(Opc, DL, VT, LHS, RHS);
} }
case ISD::SETUGE: case ISD::SETUGE:
case ISD::SETUGT: { case ISD::SETUGT: {
unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN; unsigned Opc = (LHS == True) ? ISD::UMAX : ISD::UMIN;
return DAG.getNode(Opc, DL, VT, LHS, RHS); return DAG.getNode(Opc, DL, VT, LHS, RHS);
} }
default: default:
@ -2657,11 +2662,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(COS_HW) NODE_NAME_CASE(COS_HW)
NODE_NAME_CASE(SIN_HW) NODE_NAME_CASE(SIN_HW)
NODE_NAME_CASE(FMAX_LEGACY) NODE_NAME_CASE(FMAX_LEGACY)
NODE_NAME_CASE(SMAX)
NODE_NAME_CASE(UMAX)
NODE_NAME_CASE(FMIN_LEGACY) NODE_NAME_CASE(FMIN_LEGACY)
NODE_NAME_CASE(SMIN)
NODE_NAME_CASE(UMIN)
NODE_NAME_CASE(FMAX3) NODE_NAME_CASE(FMAX3)
NODE_NAME_CASE(SMAX3) NODE_NAME_CASE(SMAX3)
NODE_NAME_CASE(UMAX3) NODE_NAME_CASE(UMAX3)
@ -2807,14 +2808,6 @@ void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
break; break;
} }
case AMDGPUISD::SMAX:
case AMDGPUISD::UMAX:
case AMDGPUISD::SMIN:
case AMDGPUISD::UMIN:
computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
KnownZero, KnownOne, DAG, Depth);
break;
case AMDGPUISD::CARRY: case AMDGPUISD::CARRY:
case AMDGPUISD::BORROW: { case AMDGPUISD::BORROW: {
KnownZero = APInt::getHighBitsSet(32, 31); KnownZero = APInt::getHighBitsSet(32, 31);

4
lib/Target/R600/AMDGPUISelLowering.h
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@ -228,11 +228,7 @@ enum NodeType : unsigned {
COS_HW, COS_HW,
SIN_HW, SIN_HW,
FMAX_LEGACY, FMAX_LEGACY,
SMAX,
UMAX,
FMIN_LEGACY, FMIN_LEGACY,
SMIN,
UMIN,
FMAX3, FMAX3,
SMAX3, SMAX3,
UMAX3, UMAX3,

10
lib/Target/R600/AMDGPUInstrInfo.td
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@ -94,16 +94,6 @@ def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
[] []
>; >;
// out = min(a, b) a and b are signed ints
def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]
>;
// out = min(a, b) a and b are unsigned ints
def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]
>;
// FIXME: TableGen doesn't like commutative instructions with more // FIXME: TableGen doesn't like commutative instructions with more
// than 2 operands. // than 2 operands.
// out = max(a, b, c) a, b and c are floats // out = max(a, b, c) a, b and c are floats

8
lib/Target/R600/R600Instructions.td
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@ -781,10 +781,10 @@ def XOR_INT : R600_2OP_Helper <0x32, "XOR_INT", xor>;
def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>; def NOT_INT : R600_1OP_Helper <0x33, "NOT_INT", not>;
def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>; def ADD_INT : R600_2OP_Helper <0x34, "ADD_INT", add>;
def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>; def SUB_INT : R600_2OP_Helper <0x35, "SUB_INT", sub>;
def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", AMDGPUsmax>; def MAX_INT : R600_2OP_Helper <0x36, "MAX_INT", smax>;
def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", AMDGPUsmin>; def MIN_INT : R600_2OP_Helper <0x37, "MIN_INT", smin>;
def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", AMDGPUumax>; def MAX_UINT : R600_2OP_Helper <0x38, "MAX_UINT", umax>;
def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", AMDGPUumin>; def MIN_UINT : R600_2OP_Helper <0x39, "MIN_UINT", umin>;
def SETE_INT : R600_2OP < def SETE_INT : R600_2OP <
0x3A, "SETE_INT", 0x3A, "SETE_INT",

20
lib/Target/R600/SIISelLowering.cpp
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@ -210,6 +210,10 @@ SITargetLowering::SITargetLowering(TargetMachine &TM,
setTargetDAGCombine(ISD::FSUB); setTargetDAGCombine(ISD::FSUB);
setTargetDAGCombine(ISD::FMINNUM); setTargetDAGCombine(ISD::FMINNUM);
setTargetDAGCombine(ISD::FMAXNUM); setTargetDAGCombine(ISD::FMAXNUM);
setTargetDAGCombine(ISD::SMIN);
setTargetDAGCombine(ISD::SMAX);
setTargetDAGCombine(ISD::UMIN);
setTargetDAGCombine(ISD::UMAX);
setTargetDAGCombine(ISD::SELECT_CC); setTargetDAGCombine(ISD::SELECT_CC);
setTargetDAGCombine(ISD::SETCC); setTargetDAGCombine(ISD::SETCC);
setTargetDAGCombine(ISD::AND); setTargetDAGCombine(ISD::AND);
@ -1633,15 +1637,15 @@ static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
switch (Opc) { switch (Opc) {
case ISD::FMAXNUM: case ISD::FMAXNUM:
return AMDGPUISD::FMAX3; return AMDGPUISD::FMAX3;
case AMDGPUISD::SMAX: case ISD::SMAX:
return AMDGPUISD::SMAX3; return AMDGPUISD::SMAX3;
case AMDGPUISD::UMAX: case ISD::UMAX:
return AMDGPUISD::UMAX3; return AMDGPUISD::UMAX3;
case ISD::FMINNUM: case ISD::FMINNUM:
return AMDGPUISD::FMIN3; return AMDGPUISD::FMIN3;
case AMDGPUISD::SMIN: case ISD::SMIN:
return AMDGPUISD::SMIN3; return AMDGPUISD::SMIN3;
case AMDGPUISD::UMIN: case ISD::UMIN:
return AMDGPUISD::UMIN3; return AMDGPUISD::UMIN3;
default: default:
llvm_unreachable("Not a min/max opcode"); llvm_unreachable("Not a min/max opcode");
@ -1727,10 +1731,10 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
return performSetCCCombine(N, DCI); return performSetCCCombine(N, DCI);
case ISD::FMAXNUM: // TODO: What about fmax_legacy? case ISD::FMAXNUM: // TODO: What about fmax_legacy?
case ISD::FMINNUM: case ISD::FMINNUM:
case AMDGPUISD::SMAX: case ISD::SMAX:
case AMDGPUISD::SMIN: case ISD::SMIN:
case AMDGPUISD::UMAX: case ISD::UMAX:
case AMDGPUISD::UMIN: { case ISD::UMIN: {
if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG && if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
N->getValueType(0) != MVT::f64 && N->getValueType(0) != MVT::f64 &&
getTargetMachine().getOptLevel() > CodeGenOpt::None) getTargetMachine().getOptLevel() > CodeGenOpt::None)

8
lib/Target/R600/SIInstructions.td
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@ -224,16 +224,16 @@ defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32",
} // End Uses = [SCC] } // End Uses = [SCC]
defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32", defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32",
[(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] [(set i32:$dst, (smin i32:$src0, i32:$src1))]
>; >;
defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32", defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32",
[(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] [(set i32:$dst, (umin i32:$src0, i32:$src1))]
>; >;
defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32", defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32",
[(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] [(set i32:$dst, (smax i32:$src0, i32:$src1))]
>; >;
defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32", defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32",
[(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] [(set i32:$dst, (umax i32:$src0, i32:$src1))]
>; >;
} // End Defs = [SCC] } // End Defs = [SCC]