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Change the X86 assembler to not require a segment register on string

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instruction's destination operand like it does for the source operand.
Also fix a typo in the comment for X86AsmParser::isSrcOp().


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152654 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2012-03-13 19:47:55 +00:00
parent 5161de6ebb
commit 0f5ab7c5f3
2 changed files with 8 additions and 4 deletions
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9
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -67,11 +67,11 @@ private:
MCStreamer &Out);
/// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi)
/// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
/// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode.
bool isSrcOp(X86Operand &Op);
/// isDstOp - Returns true if operand is either %es:(%rdi) in 64bit mode
/// or %es:(%edi) in 32bit mode.
/// isDstOp - Returns true if operand is either (%rdi) or %es:(%rdi)
/// in 64bit mode or (%edi) or %es:(%edi) in 32bit mode.
bool isDstOp(X86Operand &Op);
bool is64BitMode() const {
@ -468,7 +468,8 @@ bool X86AsmParser::isSrcOp(X86Operand &Op) {
bool X86AsmParser::isDstOp(X86Operand &Op) {
unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI;
return Op.isMem() && Op.Mem.SegReg == X86::ES &&
return Op.isMem() &&
(Op.Mem.SegReg == 0 || Op.Mem.SegReg == X86::ES) &&
isa<MCConstantExpr>(Op.Mem.Disp) &&
cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;

3
test/MC/X86/x86-64.s
View File

@ -1053,6 +1053,9 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1]
movsl
movsl %ds:(%rsi), %es:(%rdi)
movsl (%rsi), %es:(%rdi)
// rdar://10883092
// CHECK: movsd
movsl (%rsi), (%rdi)
// CHECK: movsq # encoding: [0x48,0xa5]
// CHECK: movsq