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[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR instructions.

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The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213745 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2014-07-23 12:38:17 +00:00
parent 9231148e69
commit 0f7b2e9db0
2 changed files with 30 additions and 0 deletions
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13
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5728,6 +5728,19 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
"source operands must be sequential");
return false;
}
case ARM::STR_PRE_IMM:
case ARM::STR_PRE_REG:
case ARM::STR_POST_IMM:
case ARM::STR_POST_REG: {
// Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
if (Rt == Rn)
return Error(Operands[3]->getStartLoc(),
"source register and base register can't be identical");
return false;
}
case ARM::SBFX:
case ARM::UBFX: {
// Width must be in range [1, 32-lsb].

17
test/MC/ARM/diagnostics.s
View File

@ -490,4 +490,21 @@ foo2:
@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
@ CHECK-ERRORS: ^
str r0, [r0, #4]!
str r0, [r0, r1]!
str r0, [r0], #4
str r0, [r0], r1
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0, #4]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0], #4
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: str r0, [r0], r1
@ CHECK-ERRORS: ^