diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index c5d5f61bf96..b990ecdd9ff 100644
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -64,6 +64,7 @@ protected:
   /// to request that an instruction with the given type and opcode
   /// be emitted.
   virtual unsigned FastEmit_(MVT::SimpleValueType VT,
+                             MVT::SimpleValueType RetVT,
                              ISD::NodeType Opcode);
 
   /// FastEmit_r - This method is called by target-independent code
@@ -71,6 +72,7 @@ protected:
   /// register operand be emitted.
   ///
   virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
+                              MVT::SimpleValueType RetVT,
                               ISD::NodeType Opcode, unsigned Op0);
 
   /// FastEmit_rr - This method is called by target-independent code
@@ -78,6 +80,7 @@ protected:
   /// register operands be emitted.
   ///
   virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
+                               MVT::SimpleValueType RetVT,
                                ISD::NodeType Opcode,
                                unsigned Op0, unsigned Op1);
 
@@ -86,6 +89,7 @@ protected:
   /// register and immediate operands be emitted.
   ///
   virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
+                               MVT::SimpleValueType RetVT,
                                ISD::NodeType Opcode,
                                unsigned Op0, uint64_t Imm);
 
@@ -94,6 +98,7 @@ protected:
   /// register and immediate operands be emitted.
   ///
   virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
+                                MVT::SimpleValueType RetVT,
                                 ISD::NodeType Opcode,
                                 unsigned Op0, unsigned Op1, uint64_t Imm);
 
@@ -110,6 +115,7 @@ protected:
   /// to request that an instruction with the given type, opcode, and
   /// immediate operand be emitted.
   virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
+                              MVT::SimpleValueType RetVT,
                               ISD::NodeType Opcode,
                               uint64_t Imm);
 
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 53e87d10f29..4c703ca9519 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -55,7 +55,8 @@ bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
     // Unhandled operand. Halt "fast" selection and bail.
     return false;
 
-  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
+  unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
+                                   ISDOpcode, Op0, Op1);
   if (ResultReg == 0)
     // Target-specific code wasn't able to find a machine opcode for
     // the given ISD opcode and type. Halt "fast" selection and bail.
@@ -117,9 +118,9 @@ bool FastISel::SelectGetElementPtr(Instruction *I,
       // it.
       MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
       if (IdxVT.bitsLT(VT))
-        IdxN = FastEmit_r(VT, ISD::SIGN_EXTEND, IdxN);
+        IdxN = FastEmit_r(VT, VT, ISD::SIGN_EXTEND, IdxN);
       else if (IdxVT.bitsGT(VT))
-        IdxN = FastEmit_r(VT, ISD::TRUNCATE, IdxN);
+        IdxN = FastEmit_r(VT, VT, ISD::TRUNCATE, IdxN);
       if (IdxN == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
@@ -129,7 +130,7 @@ bool FastISel::SelectGetElementPtr(Instruction *I,
       if (IdxN == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
-      N = FastEmit_rr(VT, ISD::ADD, N, IdxN);
+      N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
       if (N == 0)
         // Unhandled operand. Halt "fast" selection and bail.
         return false;
@@ -228,7 +229,8 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin,
       if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
         if (I->getType()->isInteger()) {
           MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
-          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), ISD::Constant,
+          ValueMap[I] = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
+                                   ISD::Constant,
                                    CI->getZExtValue());
           break;
         } else
@@ -286,31 +288,34 @@ FastISel::FastISel(MachineFunction &mf)
 
 FastISel::~FastISel() {}
 
-unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
+unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
-                              unsigned /*Op0*/) {
+unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
+                              ISD::NodeType, unsigned /*Op0*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
-                               unsigned /*Op0*/, unsigned /*Op0*/) {
+unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, 
+                               ISD::NodeType, unsigned /*Op0*/,
+                               unsigned /*Op0*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_i(MVT::SimpleValueType, ISD::NodeType,
-                              uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
+                              ISD::NodeType, uint64_t /*Imm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType,
-                               unsigned /*Op0*/, uint64_t /*Imm*/) {
+unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
+                               ISD::NodeType, unsigned /*Op0*/,
+                               uint64_t /*Imm*/) {
   return 0;
 }
 
-unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, ISD::NodeType,
+unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
+                                ISD::NodeType,
                                 unsigned /*Op0*/, unsigned /*Op1*/,
                                 uint64_t /*Imm*/) {
   return 0;
@@ -326,13 +331,13 @@ unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
   unsigned ResultReg = 0;
   // First check if immediate type is legal. If not, we can't use the ri form.
   if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
-    ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm);
+    ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
   if (ResultReg != 0)
     return ResultReg;
-  unsigned MaterialReg = FastEmit_i(ImmType, ISD::Constant, Imm);
+  unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
   if (MaterialReg == 0)
     return 0;
-  return FastEmit_rr(VT, Opcode, Op0, MaterialReg);
+  return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
 }
 
 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp
index bd0fc1350ca..cbff9f151d0 100644
--- a/utils/TableGen/FastISelEmitter.cpp
+++ b/utils/TableGen/FastISelEmitter.cpp
@@ -268,14 +268,16 @@ void FastISelEmitter::run(std::ostream &OS) {
         OS << "  unsigned FastEmit_" << getLegalCName(Opcode)
            << "_" << getLegalCName(getName(VT)) << "_";
         Operands.PrintManglingSuffix(OS);
-        OS << "(";
+        OS << "(MVT::SimpleValueType RetVT";
+        if (!Operands.empty())
+          OS << ", ";
         Operands.PrintParameters(OS);
         OS << ");\n";
       }
 
       OS << "  unsigned FastEmit_" << getLegalCName(Opcode) << "_";
       Operands.PrintManglingSuffix(OS);
-      OS << "(MVT::SimpleValueType VT";
+      OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
       if (!Operands.empty())
         OS << ", ";
       Operands.PrintParameters(OS);
@@ -284,7 +286,7 @@ void FastISelEmitter::run(std::ostream &OS) {
 
     OS << "  unsigned FastEmit_";
     Operands.PrintManglingSuffix(OS);
-    OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+    OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
     if (!Operands.empty())
       OS << ", ";
     Operands.PrintParameters(OS);
@@ -341,7 +343,9 @@ void FastISelEmitter::run(std::ostream &OS) {
              << getLegalCName(Opcode)
              << "_" << getLegalCName(getName(VT)) << "_";
           Operands.PrintManglingSuffix(OS);
-          OS << "(";
+          OS << "(MVT::SimpleValueType RetVT";
+          if (!Operands.empty())
+            OS << ", ";
           Operands.PrintParameters(OS);
           OS << ") {\n";
 
@@ -382,7 +386,7 @@ void FastISelEmitter::run(std::ostream &OS) {
       OS << "unsigned FastISel::FastEmit_"
          << getLegalCName(Opcode) << "_";
       Operands.PrintManglingSuffix(OS);
-      OS << "(MVT::SimpleValueType VT";
+      OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT";
       if (!Operands.empty())
         OS << ", ";
       Operands.PrintParameters(OS);
@@ -395,7 +399,9 @@ void FastISelEmitter::run(std::ostream &OS) {
         OS << "  case " << TypeName << ": return FastEmit_"
            << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
         Operands.PrintManglingSuffix(OS);
-        OS << "(";
+        OS << "(RetVT";
+        if (!Operands.empty())
+          OS << ", ";
         Operands.PrintArguments(OS);
         OS << ");\n";
       }
@@ -412,7 +418,7 @@ void FastISelEmitter::run(std::ostream &OS) {
     // on opcode and type.
     OS << "unsigned FastISel::FastEmit_";
     Operands.PrintManglingSuffix(OS);
-    OS << "(MVT::SimpleValueType VT, ISD::NodeType Opcode";
+    OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode";
     if (!Operands.empty())
       OS << ", ";
     Operands.PrintParameters(OS);
@@ -425,7 +431,7 @@ void FastISelEmitter::run(std::ostream &OS) {
       OS << "  case " << Opcode << ": return FastEmit_"
          << getLegalCName(Opcode) << "_";
       Operands.PrintManglingSuffix(OS);
-      OS << "(VT";
+      OS << "(VT, RetVT";
       if (!Operands.empty())
         OS << ", ";
       Operands.PrintArguments(OS);