From 0f899c78e18e39a8ccd08386aaa493a1b9a712a3 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Sat, 30 Oct 2010 19:38:20 +0000
Subject: [PATCH] Resolve a terrible hack in tblgen: instead of hardcoding
 "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that
 inherits from AssemblerPredicate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117831 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/Target/Target.td        | 12 +++++++++
 lib/Target/X86/X86InstrInfo.td       |  4 +--
 utils/TableGen/AsmMatcherEmitter.cpp | 40 +++++++++-------------------
 3 files changed, 26 insertions(+), 30 deletions(-)

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 2af75561ffe..87faa6b7e24 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -251,6 +251,11 @@ class Instruction {
 /// selector matching code. Currently each predicate is just a string.
 class Predicate<string cond> {
   string CondString = cond;
+  
+  /// AssemblerMatcherPredicate - If this feature can be used by the assembler
+  /// matcher, this is true.  Targets should set this by inheriting their
+  /// feature from the AssemblerPredicate class in addition to Predicate.
+  bit AssemblerMatcherPredicate = 0;
 }
 
 /// NoHonorSignDependentRounding - This predicate is true if support for
@@ -529,6 +534,13 @@ class AsmParser {
 }
 def DefaultAsmParser : AsmParser;
 
+/// AssemblerPredicate - This is a Predicate that can be used when the assembler
+/// matches instructions and aliases.
+class AssemblerPredicate {
+  bit AssemblerMatcherPredicate = 1;
+}
+
+
 
 /// MnemonicAlias - This class allows targets to define assembler mnemonic
 /// aliases.  This should be used when all forms of one mnemonic are accepted
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index c0f350adacf..3af3911ef3f 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -414,8 +414,8 @@ def HasFMA3      : Predicate<"Subtarget->hasFMA3()">;
 def HasFMA4      : Predicate<"Subtarget->hasFMA4()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
-def In32BitMode  : Predicate<"!Subtarget->is64Bit()">;
-def In64BitMode  : Predicate<"Subtarget->is64Bit()">;
+def In32BitMode  : Predicate<"!Subtarget->is64Bit()">, AssemblerPredicate;
+def In64BitMode  : Predicate<"Subtarget->is64Bit()">, AssemblerPredicate;
 def IsWin64      : Predicate<"Subtarget->isTargetWin64()">;
 def NotWin64     : Predicate<"!Subtarget->isTargetWin64()">;
 def SmallCode    : Predicate<"TM.getCodeModel() == CodeModel::Small">;
diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp
index 474319d0116..999c137109b 100644
--- a/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/utils/TableGen/AsmMatcherEmitter.cpp
@@ -963,27 +963,15 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
     }
 
     // Compute the require features.
-    ListInit *Predicates = CGI.TheDef->getValueAsListInit("Predicates");
-    for (unsigned i = 0, e = Predicates->getSize(); i != e; ++i) {
-      if (DefInit *Pred = dynamic_cast<DefInit*>(Predicates->getElement(i))) {
-        // Ignore OptForSize and OptForSpeed, they aren't really requirements,
-        // rather they are hints to isel.
-        //
-        // FIXME: Find better way to model this.
-        if (Pred->getDef()->getName() == "OptForSize" ||
-            Pred->getDef()->getName() == "OptForSpeed")
-          continue;
-
-        // FIXME: Total hack; for now, we just limit ourselves to In32BitMode
-        // and In64BitMode, because we aren't going to have the right feature
-        // masks for SSE and friends. We need to decide what we are going to do
-        // about CPU subtypes to implement this the right way.
-        if (Pred->getDef()->getName() != "In32BitMode" &&
-            Pred->getDef()->getName() != "In64BitMode")
-          continue;
-
-        II->RequiredFeatures.push_back(getSubtargetFeature(Pred->getDef()));
-      }
+    std::vector<Record*> Predicates =
+      CGI.TheDef->getValueAsListOfDefs("Predicates");
+    for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
+      Record *Pred = Predicates[i];
+      // Ignore predicates that are not intended for the assembler.
+      if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
+        continue;
+        
+      II->RequiredFeatures.push_back(getSubtargetFeature(Pred));
     }
 
     Instructions.push_back(II.take());
@@ -1523,14 +1511,10 @@ static std::string GetAliasRequiredFeatures(Record *R) {
   for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
     Record *Pred = ReqFeatures[i];
   
-    // FIXME: Total hack; for now, we just limit ourselves to In32BitMode
-    // and In64BitMode, because we aren't going to have the right feature
-    // masks for SSE and friends. We need to decide what we are going to do
-    // about CPU subtypes to implement this the right way.
-    if (Pred->getName() != "In32BitMode" &&
-        Pred->getName() != "In64BitMode")
+    // Ignore predicates that are not intended for the assembler.
+    if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
       continue;
-
+ 
     if (NumFeatures)
       Result += '|';