diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index d6260e815a7..99007cf95c5 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -68,13 +68,16 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
   if (RC == Alpha::F4RCRegisterClass)
     BuildMI(MBB, MI, TII.get(Alpha::STS))
-      .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      .addReg(SrcReg, false, false, true)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::F8RCRegisterClass)
     BuildMI(MBB, MI, TII.get(Alpha::STT))
-      .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      .addReg(SrcReg, false, false, true)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else if (RC == Alpha::GPRCRegisterClass)
     BuildMI(MBB, MI, TII.get(Alpha::STQ))
-      .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+      .addReg(SrcReg, false, false, true)
+      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else
     abort();
 }
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index 1e451c41e43..19e09caa69c 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -42,17 +42,18 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                            const TargetRegisterClass *RC) const{
 
   if (RC == IA64::FPRegisterClass) {
-    BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx).addReg(SrcReg);
+    BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
+      .addReg(SrcReg, false, false, true);
   } else if (RC == IA64::GRRegisterClass) {
-    BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(SrcReg);
- }
-  else if (RC == IA64::PRRegisterClass) {
+    BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
+      .addReg(SrcReg, false, false, true);
+  } else if (RC == IA64::PRRegisterClass) {
     /* we use IA64::r2 as a temporary register for doing this hackery. */
     // first we load 0:
     BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
     // then conditionally add 1:
     BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
-      .addImm(1).addReg(SrcReg);
+      .addImm(1).addReg(SrcReg, false, false, true);
     // and then store it to the stack
     BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
   } else assert(0 &&
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 38e57da1dd8..1dda53a342c 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -104,34 +104,34 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                      const TargetRegisterClass *RC) const {
   if (RC == PPC::GPRCRegisterClass) {
     if (SrcReg != PPC::LR) {
-      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
-                        FrameIdx);
+      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+                        .addReg(SrcReg, false, false, true), FrameIdx);
     } else {
       // FIXME: this spills LR immediately to memory in one step.  To do this,
       // we use R11, which we know cannot be used in the prolog/epilog.  This is
       // a hack.
       BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
-      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
-                        FrameIdx);
+      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+                        .addReg(PPC::R11, false, false, true), FrameIdx);
     }
   } else if (RC == PPC::G8RCRegisterClass) {
     if (SrcReg != PPC::LR8) {
-      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
-                        FrameIdx);
+      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
+                        .addReg(SrcReg, false, false, true), FrameIdx);
     } else {
       // FIXME: this spills LR immediately to memory in one step.  To do this,
       // we use R11, which we know cannot be used in the prolog/epilog.  This is
       // a hack.
       BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
-      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
-                        FrameIdx);
+      addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD))
+                        .addReg(PPC::X11, false, false, true), FrameIdx);
     }
   } else if (RC == PPC::F8RCRegisterClass) {
-    addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
-                      FrameIdx);
+    addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD))
+                      .addReg(SrcReg, false, false, true), FrameIdx);
   } else if (RC == PPC::F4RCRegisterClass) {
-    addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
-                      FrameIdx);
+    addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS))
+                      .addReg(SrcReg, false, false, true), FrameIdx);
   } else if (RC == PPC::CRRCRegisterClass) {
     // FIXME: We use R0 here, because it isn't available for RA.
     // We need to store the CR in the low 4-bits of the saved value.  First,
@@ -147,8 +147,8 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
         .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
     }
     
-    addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
-                      FrameIdx);
+    addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW))
+                      .addReg(PPC::R0, false, false, true), FrameIdx);
   } else if (RC == PPC::VRRCRegisterClass) {
     // We don't have indexed addressing for vector loads.  Emit:
     // R11 = ADDI FI#
@@ -158,7 +158,7 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
                       FrameIdx, 0, 0);
     BuildMI(MBB, MI, TII.get(PPC::STVX))
-      .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
+      .addReg(SrcReg, false, false, true).addReg(PPC::R0).addReg(PPC::R0);
   } else {
     assert(0 && "Unknown regclass!");
     abort();
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 4ea31e2e8e1..f7feb9cd50e 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -37,13 +37,13 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
   if (RC == SP::IntRegsRegisterClass)
     BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg);
+      .addReg(SrcReg, false, false, true);
   else if (RC == SP::FPRegsRegisterClass)
     BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg);
+      .addReg(SrcReg, false, false, true);
   else if (RC == SP::DFPRegsRegisterClass)
     BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
-      .addReg(SrcReg);
+      .addReg(SrcReg, false, false, true);
   else
     assert(0 && "Can't store this register to stack slot");
 }
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 75a2c7579d2..8287306053f 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -93,7 +93,8 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     assert(0 && "Unknown regclass");
     abort();
   }
-  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
+  addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
+    .addReg(SrcReg, false, false, true);
 }
 
 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,