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Make class TargetMachine the common interface to all target-dependent
information, including instr, sched, and reg information. Rename files to match the primary classes they provide. Commented out call to register allocation until more tests run correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@616 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1,3 +1,4 @@
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// $Id$
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//***************************************************************************
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// File:
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// Sparc.cpp
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@ -18,12 +19,48 @@
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#include "llvm/CodeGen/PhyRegAlloc.h"
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//***************************** Internal Functions *************************/
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//----------------------------------------------------------------------------
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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//----------------------------------------------------------------------------
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//
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TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
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//----------------------------------------------------------------------------
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// Entry point for register allocation for a module
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//----------------------------------------------------------------------------
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bool
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AllocateRegisters(Method *M, TargetMachine &TM)
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{
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if ( (M)->isExternal() ) // don't process prototypes
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return false;
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if( DEBUG_RA ) {
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cout << endl << "******************** Method "<< (M)->getName();
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cout << " ********************" <<endl;
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}
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MethodLiveVarInfo LVI(M ); // Analyze live varaibles
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LVI.analyze();
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PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
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PRA.allocateRegisters();
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if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
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return false;
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}
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//***************************** External Classes **************************/
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//---------------------------------------------------------------------------
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// class UltraSparcInstrInfo
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//
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@ -396,64 +433,42 @@ void UltraSparcRegInfo::setCallArgColor(LiveRange *const LR,
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//
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//---------------------------------------------------------------------------
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UltraSparc::UltraSparc() : TargetMachine("UltraSparc-Native"),
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InstSchedulingInfo(&InstInfo),
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RegInfo( this ) {
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UltraSparc::UltraSparc()
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: TargetMachine("UltraSparc-Native"),
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instrInfo(),
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schedInfo(&instrInfo),
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regInfo( this )
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{
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optSizeForSubWordData = 4;
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minMemOpWordSize = 8;
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maxAtomicMemOpWordSize = 8;
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zeroRegNum = RegInfo.getZeroReg(); // %g0 always gives 0 on Sparc
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}
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//----------------------------------------------------------------------------
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// Entry point for register allocation for a module
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//----------------------------------------------------------------------------
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void AllocateRegisters(Method *M, TargetMachine &TM)
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bool
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UltraSparc::compileMethod(Method *M)
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{
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if ( (M)->isExternal() ) // don't process prototypes
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return;
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if( DEBUG_RA ) {
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cout << endl << "******************** Method "<< (M)->getName();
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cout << " ********************" <<endl;
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}
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MethodLiveVarInfo LVI(M ); // Analyze live varaibles
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LVI.analyze();
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if (SelectInstructionsForMethod(M, *this))
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{
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cerr << "Instruction selection failed for method " << M->getName()
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<< "\n\n";
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return true;
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}
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PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
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PRA.allocateRegisters();
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if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
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}
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bool UltraSparc::compileMethod(Method *M) {
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if (SelectInstructionsForMethod(M, *this)) {
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cerr << "Instruction selection failed for method " << M->getName()
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<< "\n\n";
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return true;
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}
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if (ScheduleInstructionsWithSSA(M, *this))
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{
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cerr << "Instruction scheduling before allocation failed for method "
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<< M->getName() << "\n\n";
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return true;
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}
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// if (AllocateRegisters(M, *this)) // allocate registers
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// {
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// cerr << "Register allocation failed for method "
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// << M->getName() << "\n\n";
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// return true;
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// }
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if (ScheduleInstructionsWithSSA(M, *this, InstSchedulingInfo)) {
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cerr << "Instruction scheduling before allocation failed for method "
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<< M->getName() << "\n\n";
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return true;
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}
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AllocateRegisters(M, *this); // allocate registers
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return false;
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}
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