From 0fc32dae8f380f57087bf48e4248f1ad3326a1b0 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Sun, 3 May 2009 13:05:00 +0000
Subject: [PATCH] Add pattern for OR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70720 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/MSP430/MSP430ISelLowering.cpp |  1 -
 lib/Target/MSP430/MSP430ISelLowering.h   |  1 -
 lib/Target/MSP430/MSP430InstrInfo.td     | 11 +++++++++++
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp
index 39ee0756619..e7149e541ec 100644
--- a/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -54,7 +54,6 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
   setShiftAmountType(MVT::i8);
 
   setOperationAction(ISD::SRA, MVT::i16, Custom);
-
   setOperationAction(ISD::RET, MVT::Other, Custom);
 }
 
diff --git a/lib/Target/MSP430/MSP430ISelLowering.h b/lib/Target/MSP430/MSP430ISelLowering.h
index e68b3ffe9f5..d68c7a7ccf2 100644
--- a/lib/Target/MSP430/MSP430ISelLowering.h
+++ b/lib/Target/MSP430/MSP430ISelLowering.h
@@ -50,7 +50,6 @@ namespace llvm {
     SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
     SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
     SDValue LowerShifts(SDValue Op, SelectionDAG &DAG);
-
   private:
     const MSP430Subtarget &Subtarget;
     const MSP430TargetMachine &TM;
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index 6eed56deb81..d1d02dbe5eb 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -152,4 +152,15 @@ def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
                      [(set GR16:$dst, (MSP430rra GR16:$src)),
                       (implicit SR)]>;
 } // Defs = [SR]
+
+let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
+def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
+                    "bis.w\t{$src2, $dst|$dst, $src2}",
+                    [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>;
+}
+
+def OR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
+                    "bis.w\t{$src2, $dst|$dst, $src2}",
+                    [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>;
+
 } // isTwoAddress = 1