6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing

Browse Source 
the 0b10 mask encoding bits.  Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use.  Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions.  Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby
2012-05-17 22:18:01 +00:00
parent bb8cef51df
commit 0fd4f3c8de
4 changed files with 82 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
test/MC/ARM/thumb2-mclass.s
View File

@@ -44,9 +44,21 @@
@------------------------------------------------------------------------------
msr apsr, r0
msr apsr_nzcvq, r0
msr apsr_g, r0
msr apsr_nzcvqg, r0
msr iapsr, r0
msr iapsr_nzcvq, r0
msr iapsr_g, r0
msr iapsr_nzcvqg, r0
msr eapsr, r0
msr eapsr_nzcvq, r0
msr eapsr_g, r0
msr eapsr_nzcvqg, r0
msr xpsr, r0
msr xpsr_nzcvq, r0
msr xpsr_g, r0
msr xpsr_nzcvqg, r0
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
@@ -58,10 +70,22 @@
msr faultmask, r0
msr control, r0
@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x80]
@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x80]
@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x80]
@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x80]
@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]
@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84]
@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c]
@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84]
@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c]
@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80]
@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80]
@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80]