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Allow physregs to occur in the dag with multiple types. Though I don't likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point. :(

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This fixes compilation of mesa


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23161 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-30 22:38:38 +00:00
parent d6a80778e5
commit 0fdd768094
1 changed files with 8 additions and 12 deletions
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20
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -307,7 +307,8 @@ void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0;
break; break;
case ISD::Register: case ISD::Register:
RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0; RegNodes.erase(std::make_pair(cast<RegisterSDNode>(N)->getReg(),
N->getValueType(0)));
break; break;
case ISD::SRCVALUE: { case ISD::SRCVALUE: {
SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); SrcValueSDNode *SVN = cast<SrcValueSDNode>(N);
@ -533,18 +534,13 @@ SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) {
return SDOperand(CondCodeNodes[Cond], 0); return SDOperand(CondCodeNodes[Cond], 0);
} }
SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) { SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) {
if (Reg >= RegNodes.size()) RegisterSDNode *&Reg = RegNodes[std::make_pair(RegNo, VT)];
RegNodes.resize(Reg+1); if (!Reg) {
RegisterSDNode *&Result = RegNodes[Reg]; Reg = new RegisterSDNode(RegNo, VT);
if (Result) { AllNodes.push_back(Reg);
assert(Result->getValueType(0) == VT &&
"Inconsistent value types for machine registers");
} else {
Result = new RegisterSDNode(Reg, VT);
AllNodes.push_back(Result);
} }
return SDOperand(Result, 0); return SDOperand(Reg, 0);
} }
SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,