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[x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199809 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse 2014-01-22 15:08:55 +00:00
parent af588b9f0e
commit 0ff018e500
6 changed files with 31 additions and 22 deletions
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21
lib/Target/X86/AsmParser/X86AsmParser.cpp
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@ -2332,16 +2332,17 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
delete &Op;
}
}
// Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
if (Name.startswith("ins") && Operands.size() == 3 &&
(Name == "insb" || Name == "insw" || Name == "insl")) {
X86Operand &Op = *(X86Operand*)Operands.begin()[1];
X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
Operands.pop_back();
Operands.pop_back();
delete &Op;
delete &Op2;
// Append default arguments to "ins[bwld]"
if (Name.startswith("ins") && Operands.size() == 1 &&
(Name == "insb" || Name == "insw" || Name == "insl" ||
Name == "insd" )) {
if (isParsingIntelSyntax()) {
Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
Operands.push_back(DefaultMemDIOperand(NameLoc));
} else {
Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
Operands.push_back(DefaultMemDIOperand(NameLoc));
}
}

9
lib/Target/X86/X86InstrSystem.td
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@ -116,9 +116,12 @@ let Uses = [EAX] in
def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
"out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>, OpSize16;
def IN8 : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
"insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
"insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize;
def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
"ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
} // SchedRW
//===----------------------------------------------------------------------===//

5
test/MC/X86/index-operations.s
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@ -139,3 +139,8 @@ outsw %fs:(%esi), %dx
// 64: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x67,0x6f]
// 32: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x6f]
// 16: outsw %fs:(%esi), %dx # encoding: [0x64,0x67,0x6f]
insw %dx, (%edi)
// 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d]
// 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
// 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d]

6
test/MC/X86/x86-16.s
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@ -809,17 +809,17 @@ pshufw $90, %mm4, %mm0
outsl %ds:(%si), %dx
outsl (%si), %dx
// CHECK: insb # encoding: [0x6c]
// CHECK: insb %dx, %es:(%di) # encoding: [0x6c]
// CHECK: insb
insb
insb %dx, %es:(%di)
// CHECK: insw # encoding: [0x6d]
// CHECK: insw %dx, %es:(%di) # encoding: [0x6d]
// CHECK: insw
insw
insw %dx, %es:(%di)
// CHECK: insl # encoding: [0x66,0x6d]
// CHECK: insl %dx, %es:(%di) # encoding: [0x66,0x6d]
// CHECK: insl
insl
insl %dx, %es:(%di)

6
test/MC/X86/x86-32.s
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@ -885,17 +885,17 @@ pshufw $90, %mm4, %mm0
outsl %ds:(%esi), %dx
outsl (%esi), %dx
// CHECK: insb # encoding: [0x6c]
// CHECK: insb %dx, %es:(%edi) # encoding: [0x6c]
// CHECK: insb
insb
insb %dx, %es:(%edi)
// CHECK: insw # encoding: [0x66,0x6d]
// CHECK: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
// CHECK: insw
insw
insw %dx, %es:(%edi)
// CHECK: insl # encoding: [0x6d]
// CHECK: insl %dx, %es:(%edi) # encoding: [0x6d]
// CHECK: insl
insl
insl %dx, %es:(%edi)

6
test/MC/X86/x86-64.s
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@ -1070,17 +1070,17 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1]
outsl %ds:(%rsi), %dx
outsl (%rsi), %dx
// CHECK: insb # encoding: [0x6c]
// CHECK: insb %dx, %es:(%rdi) # encoding: [0x6c]
// CHECK: insb
insb
insb %dx, %es:(%rdi)
// CHECK: insw # encoding: [0x66,0x6d]
// CHECK: insw %dx, %es:(%rdi) # encoding: [0x66,0x6d]
// CHECK: insw
insw
insw %dx, %es:(%rdi)
// CHECK: insl # encoding: [0x6d]
// CHECK: insl %dx, %es:(%rdi) # encoding: [0x6d]
// CHECK: insl
insl
insl %dx, %es:(%rdi)