mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
[x86] Allow segment and address-size overrides for INS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199809 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
af588b9f0e
commit
0ff018e500
@ -2332,16 +2332,17 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
|
|||||||
delete &Op;
|
delete &Op;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
// Transform "ins[bwl] %dx, %es:(%edi)" into "ins[bwl]"
|
|
||||||
if (Name.startswith("ins") && Operands.size() == 3 &&
|
// Append default arguments to "ins[bwld]"
|
||||||
(Name == "insb" || Name == "insw" || Name == "insl")) {
|
if (Name.startswith("ins") && Operands.size() == 1 &&
|
||||||
X86Operand &Op = *(X86Operand*)Operands.begin()[1];
|
(Name == "insb" || Name == "insw" || Name == "insl" ||
|
||||||
X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
|
Name == "insd" )) {
|
||||||
if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
|
if (isParsingIntelSyntax()) {
|
||||||
Operands.pop_back();
|
Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
|
||||||
Operands.pop_back();
|
Operands.push_back(DefaultMemDIOperand(NameLoc));
|
||||||
delete &Op;
|
} else {
|
||||||
delete &Op2;
|
Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
|
||||||
|
Operands.push_back(DefaultMemDIOperand(NameLoc));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -116,9 +116,12 @@ let Uses = [EAX] in
|
|||||||
def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
||||||
"out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
|
"out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
|
||||||
|
|
||||||
def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
|
def IN8 : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
|
||||||
def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
|
"insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
|
||||||
def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>, OpSize16;
|
def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
|
||||||
|
"insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize;
|
||||||
|
def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
|
||||||
|
"ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
|
||||||
} // SchedRW
|
} // SchedRW
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
@ -139,3 +139,8 @@ outsw %fs:(%esi), %dx
|
|||||||
// 64: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x67,0x6f]
|
// 64: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x67,0x6f]
|
||||||
// 32: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x6f]
|
// 32: outsw %fs:(%esi), %dx # encoding: [0x66,0x64,0x6f]
|
||||||
// 16: outsw %fs:(%esi), %dx # encoding: [0x64,0x67,0x6f]
|
// 16: outsw %fs:(%esi), %dx # encoding: [0x64,0x67,0x6f]
|
||||||
|
|
||||||
|
insw %dx, (%edi)
|
||||||
|
// 64: insw %dx, %es:(%edi) # encoding: [0x66,0x67,0x6d]
|
||||||
|
// 32: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
|
||||||
|
// 16: insw %dx, %es:(%edi) # encoding: [0x67,0x6d]
|
||||||
|
@ -809,17 +809,17 @@ pshufw $90, %mm4, %mm0
|
|||||||
outsl %ds:(%si), %dx
|
outsl %ds:(%si), %dx
|
||||||
outsl (%si), %dx
|
outsl (%si), %dx
|
||||||
|
|
||||||
// CHECK: insb # encoding: [0x6c]
|
// CHECK: insb %dx, %es:(%di) # encoding: [0x6c]
|
||||||
// CHECK: insb
|
// CHECK: insb
|
||||||
insb
|
insb
|
||||||
insb %dx, %es:(%di)
|
insb %dx, %es:(%di)
|
||||||
|
|
||||||
// CHECK: insw # encoding: [0x6d]
|
// CHECK: insw %dx, %es:(%di) # encoding: [0x6d]
|
||||||
// CHECK: insw
|
// CHECK: insw
|
||||||
insw
|
insw
|
||||||
insw %dx, %es:(%di)
|
insw %dx, %es:(%di)
|
||||||
|
|
||||||
// CHECK: insl # encoding: [0x66,0x6d]
|
// CHECK: insl %dx, %es:(%di) # encoding: [0x66,0x6d]
|
||||||
// CHECK: insl
|
// CHECK: insl
|
||||||
insl
|
insl
|
||||||
insl %dx, %es:(%di)
|
insl %dx, %es:(%di)
|
||||||
|
@ -885,17 +885,17 @@ pshufw $90, %mm4, %mm0
|
|||||||
outsl %ds:(%esi), %dx
|
outsl %ds:(%esi), %dx
|
||||||
outsl (%esi), %dx
|
outsl (%esi), %dx
|
||||||
|
|
||||||
// CHECK: insb # encoding: [0x6c]
|
// CHECK: insb %dx, %es:(%edi) # encoding: [0x6c]
|
||||||
// CHECK: insb
|
// CHECK: insb
|
||||||
insb
|
insb
|
||||||
insb %dx, %es:(%edi)
|
insb %dx, %es:(%edi)
|
||||||
|
|
||||||
// CHECK: insw # encoding: [0x66,0x6d]
|
// CHECK: insw %dx, %es:(%edi) # encoding: [0x66,0x6d]
|
||||||
// CHECK: insw
|
// CHECK: insw
|
||||||
insw
|
insw
|
||||||
insw %dx, %es:(%edi)
|
insw %dx, %es:(%edi)
|
||||||
|
|
||||||
// CHECK: insl # encoding: [0x6d]
|
// CHECK: insl %dx, %es:(%edi) # encoding: [0x6d]
|
||||||
// CHECK: insl
|
// CHECK: insl
|
||||||
insl
|
insl
|
||||||
insl %dx, %es:(%edi)
|
insl %dx, %es:(%edi)
|
||||||
|
@ -1070,17 +1070,17 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1]
|
|||||||
outsl %ds:(%rsi), %dx
|
outsl %ds:(%rsi), %dx
|
||||||
outsl (%rsi), %dx
|
outsl (%rsi), %dx
|
||||||
|
|
||||||
// CHECK: insb # encoding: [0x6c]
|
// CHECK: insb %dx, %es:(%rdi) # encoding: [0x6c]
|
||||||
// CHECK: insb
|
// CHECK: insb
|
||||||
insb
|
insb
|
||||||
insb %dx, %es:(%rdi)
|
insb %dx, %es:(%rdi)
|
||||||
|
|
||||||
// CHECK: insw # encoding: [0x66,0x6d]
|
// CHECK: insw %dx, %es:(%rdi) # encoding: [0x66,0x6d]
|
||||||
// CHECK: insw
|
// CHECK: insw
|
||||||
insw
|
insw
|
||||||
insw %dx, %es:(%rdi)
|
insw %dx, %es:(%rdi)
|
||||||
|
|
||||||
// CHECK: insl # encoding: [0x6d]
|
// CHECK: insl %dx, %es:(%rdi) # encoding: [0x6d]
|
||||||
// CHECK: insl
|
// CHECK: insl
|
||||||
insl
|
insl
|
||||||
insl %dx, %es:(%rdi)
|
insl %dx, %es:(%rdi)
|
||||||
|
Loading…
Reference in New Issue
Block a user