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https://github.com/c64scene-ar/llvm-6502.git
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[NVPTX] Add support for selecting CUDA vs OCL mode based on triple
IR for CUDA should use "nvptx[64]-nvidia-cuda", and IR for NV OpenCL should use "nvptx[64]-nvidia-nvcl" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184579 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -81,7 +81,8 @@ public:
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BGP,
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BGP,
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BGQ,
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BGQ,
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Freescale,
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Freescale,
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IBM
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IBM,
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NVIDIA
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};
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};
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enum OSType {
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enum OSType {
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UnknownOS,
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UnknownOS,
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@@ -107,7 +108,9 @@ public:
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NaCl, // Native Client
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NaCl, // Native Client
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CNK, // BG/P Compute-Node Kernel
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CNK, // BG/P Compute-Node Kernel
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Bitrig,
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Bitrig,
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AIX
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AIX,
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CUDA, // NVIDIA CUDA
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NVCL // NVIDIA OpenCL
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};
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};
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enum EnvironmentType {
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enum EnvironmentType {
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UnknownEnvironment,
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UnknownEnvironment,
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@@ -104,6 +104,7 @@ const char *Triple::getVendorTypeName(VendorType Kind) {
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case BGQ: return "bgq";
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case BGQ: return "bgq";
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case Freescale: return "fsl";
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case Freescale: return "fsl";
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case IBM: return "ibm";
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case IBM: return "ibm";
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case NVIDIA: return "nvidia";
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}
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}
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llvm_unreachable("Invalid VendorType!");
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llvm_unreachable("Invalid VendorType!");
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@@ -135,6 +136,8 @@ const char *Triple::getOSTypeName(OSType Kind) {
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case CNK: return "cnk";
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case CNK: return "cnk";
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case Bitrig: return "bitrig";
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case Bitrig: return "bitrig";
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case AIX: return "aix";
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case AIX: return "aix";
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case CUDA: return "cuda";
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case NVCL: return "nvcl";
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}
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}
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llvm_unreachable("Invalid OSType");
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llvm_unreachable("Invalid OSType");
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@@ -260,6 +263,7 @@ static Triple::VendorType parseVendor(StringRef VendorName) {
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.Case("bgq", Triple::BGQ)
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.Case("bgq", Triple::BGQ)
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.Case("fsl", Triple::Freescale)
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.Case("fsl", Triple::Freescale)
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.Case("ibm", Triple::IBM)
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.Case("ibm", Triple::IBM)
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.Case("nvidia", Triple::NVIDIA)
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.Default(Triple::UnknownVendor);
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.Default(Triple::UnknownVendor);
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}
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}
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@@ -287,6 +291,8 @@ static Triple::OSType parseOS(StringRef OSName) {
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.StartsWith("cnk", Triple::CNK)
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.StartsWith("cnk", Triple::CNK)
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.StartsWith("bitrig", Triple::Bitrig)
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.StartsWith("bitrig", Triple::Bitrig)
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.StartsWith("aix", Triple::AIX)
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.StartsWith("aix", Triple::AIX)
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.StartsWith("cuda", Triple::CUDA)
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.StartsWith("nvcl", Triple::NVCL)
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.Default(Triple::UnknownOS);
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.Default(Triple::UnknownOS);
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}
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}
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@@ -77,8 +77,7 @@ extern Target TheNVPTXTarget64;
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namespace NVPTX {
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namespace NVPTX {
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enum DrvInterface {
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enum DrvInterface {
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NVCL,
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NVCL,
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CUDA,
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CUDA
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TEST
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};
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};
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// A field inside TSFlags needs a shift and a mask. The usage is
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// A field inside TSFlags needs a shift and a mask. The usage is
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@@ -19,23 +19,18 @@
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using namespace llvm;
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using namespace llvm;
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// Select Driver Interface
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#include "llvm/Support/CommandLine.h"
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namespace {
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cl::opt<NVPTX::DrvInterface> DriverInterface(
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cl::desc("Choose driver interface:"),
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cl::values(clEnumValN(NVPTX::NVCL, "drvnvcl", "Nvidia OpenCL driver"),
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clEnumValN(NVPTX::CUDA, "drvcuda", "Nvidia CUDA driver"),
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clEnumValN(NVPTX::TEST, "drvtest", "Plain Test"), clEnumValEnd),
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cl::init(NVPTX::NVCL));
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}
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NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
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NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool is64Bit)
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const std::string &FS, bool is64Bit)
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: NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),
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: NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0),
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SmVersion(20) {
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SmVersion(20) {
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drvInterface = DriverInterface;
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Triple T(TT);
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if (T.getOS() == Triple::NVCL)
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drvInterface = NVPTX::NVCL;
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else
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drvInterface = NVPTX::CUDA;
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// Provide the default CPU if none
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// Provide the default CPU if none
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std::string defCPU = "sm_20";
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std::string defCPU = "sm_20";
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@@ -1,6 +1,7 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target triple = "nvptx-nvidia-cuda"
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; Ensure global variables in address space 0 are promoted to address space 1
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; Ensure global variables in address space 0 are promoted to address space 1
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@@ -1,7 +1,7 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target triple = "nvptx-nvidia-cuda"
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; CHECK: .visible .global .align 1 .u8 mypred
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; CHECK: .visible .global .align 1 .u8 mypred
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@mypred = addrspace(1) global i1 true, align 1
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@mypred = addrspace(1) global i1 true, align 1
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@@ -1,6 +1,7 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target triple = "nvptx-nvidia-cuda"
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; Make sure predicate (i1) operands to kernels get expanded out to .u8
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; Make sure predicate (i1) operands to kernels get expanded out to .u8
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@@ -1,7 +1,7 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target triple = "nvptx-nvidia-cuda"
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define void @main(i1* %a1, i32 %a2, i32* %arg3) {
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define void @main(i1* %a1, i32 %a2, i32* %arg3) {
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; CHECK: ld.u8
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; CHECK: ld.u8
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@@ -1,4 +1,6 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target triple = "nvptx-nvidia-cuda"
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; Function Attrs: nounwind
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; Function Attrs: nounwind
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; CHECK: .entry foo
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; CHECK: .entry foo
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