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Not all PPC functions with a frame pointer need a RS spill slot

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We used to add a spill slot for the register scavenger whenever the function
has a frame pointer. This is unnecessarily conservative: We may need the spill
slot for dynamic stack allocations, and functions with dynamic stack
allocations always have a FP, but we might also have a FP for other reasons
(such as the user explicitly disabling frame-pointer elimination), and we don't
necessarily need a spill slot for those functions.

The structsinregs test needed adjustment because it disables FP elimination.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-03-14 19:34:32 +00:00
parent d81511f0a6
commit 100a94bc93
2 changed files with 11 additions and 11 deletions
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2
lib/Target/PowerPC/PPCFrameLowering.cpp
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@ -831,7 +831,7 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// r0 for now. // r0 for now.
if (RegInfo->requiresRegisterScavenging(MF)) if (RegInfo->requiresRegisterScavenging(MF))
if (needsFP(MF) || spillsCR(MF)) { if (MFI->hasVarSizedObjects() || spillsCR(MF)) {
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;

20
test/CodeGen/PowerPC/structsinregs.ll
View File

@ -63,13 +63,13 @@ entry:
%call = call i32 @callee1(%struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7) %call = call i32 @callee1(%struct.s1* byval %p1, %struct.s2* byval %p2, %struct.s3* byval %p3, %struct.s4* byval %p4, %struct.s5* byval %p5, %struct.s6* byval %p6, %struct.s7* byval %p7)
ret i32 %call ret i32 %call
; CHECK: ld 9, 128(31) ; CHECK: ld 9, 112(31)
; CHECK: ld 8, 136(31) ; CHECK: ld 8, 120(31)
; CHECK: ld 7, 144(31) ; CHECK: ld 7, 128(31)
; CHECK: lwz 6, 152(31) ; CHECK: lwz 6, 136(31)
; CHECK: lwz 5, 160(31) ; CHECK: lwz 5, 144(31)
; CHECK: lhz 4, 168(31) ; CHECK: lhz 4, 152(31)
; CHECK: lbz 3, 176(31) ; CHECK: lbz 3, 160(31)
} }
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
@ -155,10 +155,10 @@ entry:
; CHECK: ld 9, 96(1) ; CHECK: ld 9, 96(1)
; CHECK: ld 8, 88(1) ; CHECK: ld 8, 88(1)
; CHECK: ld 7, 80(1) ; CHECK: ld 7, 80(1)
; CHECK: lwz 6, 152(31) ; CHECK: lwz 6, 136(31)
; CHECK: ld 5, 64(1) ; CHECK: ld 5, 64(1)
; CHECK: lhz 4, 168(31) ; CHECK: lhz 4, 152(31)
; CHECK: lbz 3, 176(31) ; CHECK: lbz 3, 160(31)
} }
define internal i32 @callee2(%struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind { define internal i32 @callee2(%struct.t1* byval %v1, %struct.t2* byval %v2, %struct.t3* byval %v3, %struct.t4* byval %v4, %struct.t5* byval %v5, %struct.t6* byval %v6, %struct.t7* byval %v7) nounwind {