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ADC and IMUL are also commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19264 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -928,8 +928,10 @@ let isTwoAddress = 0 in {
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"add{l} {$src2, $dst|$dst, $src2}">;
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}
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let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
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def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
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"adc{l} {$src2, $dst|$dst, $src2}">;
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}
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def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2),
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"adc{l} {$src2, $dst|$dst, $src2}">;
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def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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@ -1020,10 +1022,12 @@ def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
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def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
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def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
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"imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
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def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
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"imul{l} {$src2, $dst|$dst, $src2}">, TB;
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}
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def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2),
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"imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize;
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def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
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