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Minor wording tweak for memory model.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136668 91177308-0d34-0410-b5e6-96231b3b80d8
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Eli Friedman 2011-08-02 01:15:34 +00:00
parent 9b0a479bb7
commit 101c81da45
1 changed files with 4 additions and 4 deletions
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docs/LangRef.html
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@ -1555,10 +1555,10 @@ emit more than one instruction to read the series of bytes.</p>
<p>Note that in cases where none of the atomic intrinsics are used, this model
places only one restriction on IR transformations on top of what is required
for single-threaded execution: introducing a store to a byte which might not
otherwise be stored to can introduce undefined behavior. (Specifically, in
the case where another thread might write to and read from an address,
introducing a store can change a load that may see exactly one write into
a load that may see multiple writes.)</p>
otherwise be stored is not allowed in general. (Specifically, in the case
where another thread might write to and read from an address, introducing a
store can change a load that may see exactly one write into a load that may
see multiple writes.)</p>
<!-- FIXME: This model assumes all targets where concurrency is relevant have
a byte-size store which doesn't affect adjacent bytes. As far as I can tell,