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ARM STR_POST_IMM offset encoding fix in load/store optimizer.
Tidy up the code a bit and push the definition of the value next to the uses to try to minimize this sort of issue from arising again while I'm at it. rdar://9945172 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137525 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -893,15 +893,6 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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if (!DoMerge)
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return false;
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unsigned Offset = 0;
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// FIXME: Loads still use a combined reg/imm offset operand. When
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// AM2 refactoring is complete, this can go away and just always use
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// the raw Offset value.
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if (isAM2 && isLd)
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Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
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else if (!isAM5)
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Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
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if (isAM5) {
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// VLDM[SD}_UPD, VSTM[SD]_UPD
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// (There are no base-updating versions of VLDR/VSTR instructions, but the
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@ -915,31 +906,37 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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.addReg(MO.getReg(), (isLd ? getDefRegState(true) :
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getKillRegState(MO.isKill())));
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} else if (isLd) {
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if (isAM2)
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if (isAM2) {
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int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
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// LDR_PRE, LDR_POST,
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BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
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.addReg(Base, RegState::Define)
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.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
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else
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} else {
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int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
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// t2LDR_PRE, t2LDR_POST
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BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg())
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.addReg(Base, RegState::Define)
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.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
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}
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} else {
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MachineOperand &MO = MI->getOperand(0);
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// FIXME: post-indexed stores use am2offset_imm, which still encodes
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// the vestigal zero-reg offset register. When that's fixed, this clause
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// can be removed entirely.
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if (isAM2 && NewOpc == ARM::STR_POST_IMM)
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if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
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int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
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// STR_PRE, STR_POST
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BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
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.addReg(MO.getReg(), getKillRegState(MO.isKill()))
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.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
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else
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} else {
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int Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
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// t2STR_PRE, t2STR_POST
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BuildMI(MBB, MBBI, dl, TII->get(NewOpc), Base)
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.addReg(MO.getReg(), getKillRegState(MO.isKill()))
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.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
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}
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}
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MBB.erase(MBBI);
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