From 103683c4cb8b11ed506f73353f84efd22618510e Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Tue, 1 Apr 2014 12:22:20 +0000 Subject: [PATCH] Fixing warnings in the MSVC build. No functional changes intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205301 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM64/ARM64FastISel.cpp | 2 +- lib/Target/ARM64/ARM64ISelLowering.cpp | 6 +-- lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 12 ++--- .../ARM64/Disassembler/ARM64Disassembler.cpp | 4 +- .../ARM64/MCTargetDesc/ARM64AddressingModes.h | 54 +++++++++---------- 5 files changed, 39 insertions(+), 39 deletions(-) diff --git a/lib/Target/ARM64/ARM64FastISel.cpp b/lib/Target/ARM64/ARM64FastISel.cpp index 1561e25f1eb..51b0f7613ff 100644 --- a/lib/Target/ARM64/ARM64FastISel.cpp +++ b/lib/Target/ARM64/ARM64FastISel.cpp @@ -1918,7 +1918,7 @@ bool ARM64FastISel::TargetSelectInstruction(const Instruction *I) { } return false; // Silence warnings. - (void)CC_ARM64_DarwinPCS_VarArg; + (void)&CC_ARM64_DarwinPCS_VarArg; } namespace llvm { diff --git a/lib/Target/ARM64/ARM64ISelLowering.cpp b/lib/Target/ARM64/ARM64ISelLowering.cpp index 5bd7b47c772..b6672ee0d7f 100644 --- a/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -1740,9 +1740,9 @@ static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) { } // built the mask value encoding the expected behavior. - unsigned PrfOp = (IsWrite << 4) | // Load/Store bit - (Locality << 1) | // Cache level bits - IsStream; // Stream bit + unsigned PrfOp = (IsWrite << 4) | // Load/Store bit + (Locality << 1) | // Cache level bits + (unsigned)IsStream; // Stream bit return DAG.getNode(ARM64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0), DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1)); } diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index 705d192356e..38a61d809d5 100644 --- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -3021,17 +3021,17 @@ bool ARM64AsmParser::tryParseVectorRegister(OperandVector &Operands) { const MCExpr *ImmVal; if (getParser().parseExpression(ImmVal)) - return MatchOperand_ParseFail; + return false; const MCConstantExpr *MCE = dyn_cast(ImmVal); if (!MCE) { TokError("immediate value expected for vector index"); - return MatchOperand_ParseFail; + return false; } SMLoc E = getLoc(); if (Parser.getTok().isNot(AsmToken::RBrac)) { Error(E, "']' expected"); - return MatchOperand_ParseFail; + return false; } Parser.Lex(); // Eat right bracket token. @@ -3401,17 +3401,17 @@ bool ARM64AsmParser::parseVectorList(OperandVector &Operands) { const MCExpr *ImmVal; if (getParser().parseExpression(ImmVal)) - return MatchOperand_ParseFail; + return false; const MCConstantExpr *MCE = dyn_cast(ImmVal); if (!MCE) { TokError("immediate value expected for vector index"); - return MatchOperand_ParseFail; + return false; } SMLoc E = getLoc(); if (Parser.getTok().isNot(AsmToken::RBrac)) { Error(E, "']' expected"); - return MatchOperand_ParseFail; + return false; } Parser.Lex(); // Eat right bracket token. diff --git a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp index 1af8b2f498c..44c501f76b3 100644 --- a/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp +++ b/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp @@ -1537,7 +1537,7 @@ static DecodeStatus DecodeUnconditionalBranch(llvm::MCInst &Inst, uint32_t insn, if (imm & (1 << (26 - 1))) imm |= ~((1LL << 26) - 1); - if (!Dis->tryAddingSymbolicOperand(Addr, imm << 2, Success, 4, Inst)) + if (!Dis->tryAddingSymbolicOperand(Addr, imm << 2, true, 4, Inst)) Inst.addOperand(MCOperand::CreateImm(imm)); return Success; @@ -1571,7 +1571,7 @@ static DecodeStatus DecodeTestAndBranch(llvm::MCInst &Inst, uint32_t insn, DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); Inst.addOperand(MCOperand::CreateImm(bit)); - if (!Dis->tryAddingSymbolicOperand(Addr, dst << 2, Success, 4, Inst)) + if (!Dis->tryAddingSymbolicOperand(Addr, dst << 2, true, 4, Inst)) Inst.addOperand(MCOperand::CreateImm(dst)); return Success; diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h b/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h index 75d0ee129ce..7717743b954 100644 --- a/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h +++ b/lib/Target/ARM64/MCTargetDesc/ARM64AddressingModes.h @@ -612,16 +612,16 @@ static inline bool isAdvSIMDModImmType10(uint64_t Imm) { } static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) { - bool BitA = Imm & 0xff00000000000000ULL; - bool BitB = Imm & 0x00ff000000000000ULL; - bool BitC = Imm & 0x0000ff0000000000ULL; - bool BitD = Imm & 0x000000ff00000000ULL; - bool BitE = Imm & 0x00000000ff000000ULL; - bool BitF = Imm & 0x0000000000ff0000ULL; - bool BitG = Imm & 0x000000000000ff00ULL; - bool BitH = Imm & 0x00000000000000ffULL; + uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0; + uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0; + uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0; + uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0; + uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0; + uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0; + uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0; + uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0; - unsigned EncVal = BitA; + uint8_t EncVal = BitA; EncVal <<= 1; EncVal |= BitB; EncVal <<= 1; @@ -661,16 +661,16 @@ static inline bool isAdvSIMDModImmType11(uint64_t Imm) { } static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) { - bool BitA = (Imm & 0x80000000ULL); - bool BitB = (Imm & 0x20000000ULL); - bool BitC = (Imm & 0x01000000ULL); - bool BitD = (Imm & 0x00800000ULL); - bool BitE = (Imm & 0x00400000ULL); - bool BitF = (Imm & 0x00200000ULL); - bool BitG = (Imm & 0x00100000ULL); - bool BitH = (Imm & 0x00080000ULL); + uint8_t BitA = (Imm & 0x80000000ULL) != 0; + uint8_t BitB = (Imm & 0x20000000ULL) != 0; + uint8_t BitC = (Imm & 0x01000000ULL) != 0; + uint8_t BitD = (Imm & 0x00800000ULL) != 0; + uint8_t BitE = (Imm & 0x00400000ULL) != 0; + uint8_t BitF = (Imm & 0x00200000ULL) != 0; + uint8_t BitG = (Imm & 0x00100000ULL) != 0; + uint8_t BitH = (Imm & 0x00080000ULL) != 0; - unsigned EncVal = BitA; + uint8_t EncVal = BitA; EncVal <<= 1; EncVal |= BitB; EncVal <<= 1; @@ -710,16 +710,16 @@ static inline bool isAdvSIMDModImmType12(uint64_t Imm) { } static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) { - bool BitA = (Imm & 0x8000000000000000ULL); - bool BitB = (Imm & 0x0040000000000000ULL); - bool BitC = (Imm & 0x0020000000000000ULL); - bool BitD = (Imm & 0x0010000000000000ULL); - bool BitE = (Imm & 0x0008000000000000ULL); - bool BitF = (Imm & 0x0004000000000000ULL); - bool BitG = (Imm & 0x0002000000000000ULL); - bool BitH = (Imm & 0x0001000000000000ULL); + uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0; + uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0; + uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0; + uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0; + uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0; + uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0; + uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0; + uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0; - unsigned EncVal = BitA; + uint8_t EncVal = BitA; EncVal <<= 1; EncVal |= BitB; EncVal <<= 1;