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Redirect DataLayout from TargetMachine to Module in ComputeValueVTs()
Summary: Avoid using the TargetMachine owned DataLayout and use the Module owned one instead. This requires passing the DataLayout up the stack to ComputeValueVTs(). This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, yaron.keren, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D11019 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241773 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -64,7 +64,7 @@ inline unsigned ComputeLinearIndex(Type *Ty,
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/// If Offsets is non-null, it points to a vector to be filled in
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/// If Offsets is non-null, it points to a vector to be filled in
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/// with the in-memory offsets of each of the individual values.
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/// with the in-memory offsets of each of the individual values.
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///
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///
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void ComputeValueVTs(const TargetLowering &TLI, Type *Ty,
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void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty,
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SmallVectorImpl<EVT> &ValueVTs,
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SmallVectorImpl<EVT> &ValueVTs,
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SmallVectorImpl<uint64_t> *Offsets = nullptr,
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SmallVectorImpl<uint64_t> *Offsets = nullptr,
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uint64_t StartingOffset = 0);
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uint64_t StartingOffset = 0);
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@ -2819,9 +2819,9 @@ public:
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/// Given an LLVM IR type and return type attributes, compute the return value
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/// Given an LLVM IR type and return type attributes, compute the return value
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/// EVTs and flags, and optionally also the offsets, if the return value is
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/// EVTs and flags, and optionally also the offsets, if the return value is
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/// being lowered to memory.
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/// being lowered to memory.
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void GetReturnInfo(Type* ReturnType, AttributeSet attr,
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void GetReturnInfo(Type *ReturnType, AttributeSet attr,
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SmallVectorImpl<ISD::OutputArg> &Outs,
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SmallVectorImpl<ISD::OutputArg> &Outs,
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const TargetLowering &TLI);
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const TargetLowering &TLI, const DataLayout &DL);
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} // end llvm namespace
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} // end llvm namespace
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@ -81,27 +81,27 @@ unsigned llvm::ComputeLinearIndex(Type *Ty,
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/// If Offsets is non-null, it points to a vector to be filled in
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/// If Offsets is non-null, it points to a vector to be filled in
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/// with the in-memory offsets of each of the individual values.
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/// with the in-memory offsets of each of the individual values.
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///
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///
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void llvm::ComputeValueVTs(const TargetLowering &TLI, Type *Ty,
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void llvm::ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL,
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SmallVectorImpl<EVT> &ValueVTs,
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Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
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SmallVectorImpl<uint64_t> *Offsets,
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SmallVectorImpl<uint64_t> *Offsets,
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uint64_t StartingOffset) {
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uint64_t StartingOffset) {
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// Given a struct type, recursively traverse the elements.
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// Given a struct type, recursively traverse the elements.
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if (StructType *STy = dyn_cast<StructType>(Ty)) {
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if (StructType *STy = dyn_cast<StructType>(Ty)) {
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const StructLayout *SL = TLI.getDataLayout()->getStructLayout(STy);
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const StructLayout *SL = DL.getStructLayout(STy);
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for (StructType::element_iterator EB = STy->element_begin(),
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for (StructType::element_iterator EB = STy->element_begin(),
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EI = EB,
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EI = EB,
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EE = STy->element_end();
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EE = STy->element_end();
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EI != EE; ++EI)
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EI != EE; ++EI)
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ComputeValueVTs(TLI, *EI, ValueVTs, Offsets,
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ComputeValueVTs(TLI, DL, *EI, ValueVTs, Offsets,
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StartingOffset + SL->getElementOffset(EI - EB));
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StartingOffset + SL->getElementOffset(EI - EB));
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return;
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return;
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}
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}
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// Given an array type, recursively traverse the elements.
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// Given an array type, recursively traverse the elements.
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if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
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if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
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Type *EltTy = ATy->getElementType();
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Type *EltTy = ATy->getElementType();
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uint64_t EltSize = TLI.getDataLayout()->getTypeAllocSize(EltTy);
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uint64_t EltSize = DL.getTypeAllocSize(EltTy);
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for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
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for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
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ComputeValueVTs(TLI, EltTy, ValueVTs, Offsets,
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ComputeValueVTs(TLI, DL, EltTy, ValueVTs, Offsets,
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StartingOffset + i * EltSize);
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StartingOffset + i * EltSize);
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return;
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return;
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}
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}
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@ -908,10 +908,10 @@ bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
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// Handle the incoming return values from the call.
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// Handle the incoming return values from the call.
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CLI.clearIns();
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CLI.clearIns();
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SmallVector<EVT, 4> RetTys;
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SmallVector<EVT, 4> RetTys;
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ComputeValueVTs(TLI, CLI.RetTy, RetTys);
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ComputeValueVTs(TLI, DL, CLI.RetTy, RetTys);
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SmallVector<ISD::OutputArg, 4> Outs;
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SmallVector<ISD::OutputArg, 4> Outs;
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GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI);
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GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
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bool CanLowerReturn = TLI.CanLowerReturn(
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bool CanLowerReturn = TLI.CanLowerReturn(
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CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
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CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
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@ -1480,7 +1480,7 @@ bool FastISel::selectExtractValue(const User *U) {
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unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
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unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
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SmallVector<EVT, 4> AggValueVTs;
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SmallVector<EVT, 4> AggValueVTs;
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ComputeValueVTs(TLI, AggTy, AggValueVTs);
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ComputeValueVTs(TLI, DL, AggTy, AggValueVTs);
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for (unsigned i = 0; i < VTIndex; i++)
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for (unsigned i = 0; i < VTIndex; i++)
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ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
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ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
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@ -90,7 +90,8 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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// Check whether the function can return without sret-demotion.
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// Check whether the function can return without sret-demotion.
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SmallVector<ISD::OutputArg, 4> Outs;
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SmallVector<ISD::OutputArg, 4> Outs;
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GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
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GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
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mf.getDataLayout());
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CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
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CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
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Fn->isVarArg(), Outs, Fn->getContext());
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Fn->isVarArg(), Outs, Fn->getContext());
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@ -236,7 +237,7 @@ void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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assert(PHIReg && "PHI node does not have an assigned virtual register!");
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assert(PHIReg && "PHI node does not have an assigned virtual register!");
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
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ComputeValueVTs(*TLI, MF->getDataLayout(), PN->getType(), ValueVTs);
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for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
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for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
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EVT VT = ValueVTs[vti];
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EVT VT = ValueVTs[vti];
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unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
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unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
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@ -366,7 +367,7 @@ unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
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const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
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const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(*TLI, Ty, ValueVTs);
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ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
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unsigned FirstReg = 0;
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unsigned FirstReg = 0;
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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@ -413,7 +414,7 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
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return;
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return;
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SmallVector<EVT, 1> ValueVTs;
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SmallVector<EVT, 1> ValueVTs;
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ComputeValueVTs(*TLI, Ty, ValueVTs);
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ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
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assert(ValueVTs.size() == 1 &&
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assert(ValueVTs.size() == 1 &&
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"PHIs with non-vector integer types should have a single VT.");
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"PHIs with non-vector integer types should have a single VT.");
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EVT IntVT = ValueVTs[0];
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EVT IntVT = ValueVTs[0];
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@ -588,14 +588,14 @@ RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
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EVT valuevt)
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EVT valuevt)
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: ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
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: ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
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RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &tli,
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RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
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unsigned Reg, Type *Ty) {
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const DataLayout &DL, unsigned Reg, Type *Ty) {
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ComputeValueVTs(tli, Ty, ValueVTs);
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ComputeValueVTs(TLI, DL, Ty, ValueVTs);
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT ValueVT = ValueVTs[Value];
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EVT ValueVT = ValueVTs[Value];
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unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
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unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
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MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
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MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
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for (unsigned i = 0; i != NumRegs; ++i)
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for (unsigned i = 0; i != NumRegs; ++i)
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Regs.push_back(Reg + i);
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Regs.push_back(Reg + i);
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RegVTs.push_back(RegisterVT);
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RegVTs.push_back(RegisterVT);
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@ -964,8 +964,8 @@ SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
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if (It != FuncInfo.ValueMap.end()) {
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if (It != FuncInfo.ValueMap.end()) {
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unsigned InReg = It->second;
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unsigned InReg = It->second;
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RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
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RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
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Ty);
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DAG.getDataLayout(), InReg, Ty);
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SDValue Chain = DAG.getEntryNode();
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SDValue Chain = DAG.getEntryNode();
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Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
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Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
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resolveDanglingDebugInfo(V, Result);
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resolveDanglingDebugInfo(V, Result);
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@ -1095,7 +1095,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
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"Unknown struct or array constant!");
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"Unknown struct or array constant!");
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(TLI, C->getType(), ValueVTs);
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ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
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unsigned NumElts = ValueVTs.size();
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unsigned NumElts = ValueVTs.size();
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if (NumElts == 0)
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if (NumElts == 0)
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return SDValue(); // empty struct
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return SDValue(); // empty struct
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@ -1153,7 +1153,8 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
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// If this is an instruction which fast-isel has deferred, select it now.
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// If this is an instruction which fast-isel has deferred, select it now.
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if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
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if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
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unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
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unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
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RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
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RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
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Inst->getType());
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SDValue Chain = DAG.getEntryNode();
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SDValue Chain = DAG.getEntryNode();
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return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
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return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
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}
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}
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@ -1163,6 +1164,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
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void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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auto &DL = DAG.getDataLayout();
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SDValue Chain = getControlRoot();
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SDValue Chain = getControlRoot();
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SmallVector<ISD::OutputArg, 8> Outs;
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SmallVector<ISD::OutputArg, 8> Outs;
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SmallVector<SDValue, 8> OutVals;
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SmallVector<SDValue, 8> OutVals;
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@ -1175,7 +1177,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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// Leave Outs empty so that LowerReturn won't try to load return
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// Leave Outs empty so that LowerReturn won't try to load return
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// registers the usual way.
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// registers the usual way.
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SmallVector<EVT, 1> PtrValueVTs;
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SmallVector<EVT, 1> PtrValueVTs;
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ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
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ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
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PtrValueVTs);
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PtrValueVTs);
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SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
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SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
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@ -1183,7 +1185,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<uint64_t, 4> Offsets;
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SmallVector<uint64_t, 4> Offsets;
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ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
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ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
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unsigned NumValues = ValueVTs.size();
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unsigned NumValues = ValueVTs.size();
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SmallVector<SDValue, 4> Chains(NumValues);
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SmallVector<SDValue, 4> Chains(NumValues);
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@ -1203,7 +1205,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
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MVT::Other, Chains);
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MVT::Other, Chains);
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} else if (I.getNumOperands() != 0) {
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} else if (I.getNumOperands() != 0) {
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
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ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
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unsigned NumValues = ValueVTs.size();
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unsigned NumValues = ValueVTs.size();
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if (NumValues) {
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if (NumValues) {
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SDValue RetOp = getValue(I.getOperand(0));
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SDValue RetOp = getValue(I.getOperand(0));
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@ -2012,7 +2014,7 @@ void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
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SmallVector<EVT, 2> ValueVTs;
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SmallVector<EVT, 2> ValueVTs;
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SDLoc dl = getCurSDLoc();
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SDLoc dl = getCurSDLoc();
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ComputeValueVTs(TLI, LP.getType(), ValueVTs);
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ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
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assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
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assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
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// Get the two live-in registers as SDValues. The physregs have already been
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// Get the two live-in registers as SDValues. The physregs have already been
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@ -2276,7 +2278,8 @@ void SelectionDAGBuilder::visitFCmp(const User &I) {
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void SelectionDAGBuilder::visitSelect(const User &I) {
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void SelectionDAGBuilder::visitSelect(const User &I) {
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SmallVector<EVT, 4> ValueVTs;
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
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ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
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ValueVTs);
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unsigned NumValues = ValueVTs.size();
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unsigned NumValues = ValueVTs.size();
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if (NumValues == 0) return;
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if (NumValues == 0) return;
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@ -2675,9 +2678,9 @@ void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SmallVector<EVT, 4> AggValueVTs;
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SmallVector<EVT, 4> AggValueVTs;
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ComputeValueVTs(TLI, AggTy, AggValueVTs);
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ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
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SmallVector<EVT, 4> ValValueVTs;
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SmallVector<EVT, 4> ValValueVTs;
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ComputeValueVTs(TLI, ValTy, ValValueVTs);
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ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
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unsigned NumAggValues = AggValueVTs.size();
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unsigned NumAggValues = AggValueVTs.size();
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unsigned NumValValues = ValValueVTs.size();
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unsigned NumValValues = ValValueVTs.size();
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@ -2721,7 +2724,7 @@ void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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SmallVector<EVT, 4> ValValueVTs;
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SmallVector<EVT, 4> ValValueVTs;
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ComputeValueVTs(TLI, ValTy, ValValueVTs);
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ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
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unsigned NumValValues = ValValueVTs.size();
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unsigned NumValValues = ValValueVTs.size();
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@ -2897,7 +2900,7 @@ void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
|
|||||||
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
SmallVector<uint64_t, 4> Offsets;
|
SmallVector<uint64_t, 4> Offsets;
|
||||||
ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
|
ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
|
||||||
unsigned NumValues = ValueVTs.size();
|
unsigned NumValues = ValueVTs.size();
|
||||||
if (NumValues == 0)
|
if (NumValues == 0)
|
||||||
return;
|
return;
|
||||||
@ -2974,8 +2977,8 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
|
|||||||
|
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
SmallVector<uint64_t, 4> Offsets;
|
SmallVector<uint64_t, 4> Offsets;
|
||||||
ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
|
ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
|
||||||
ValueVTs, &Offsets);
|
SrcV->getType(), ValueVTs, &Offsets);
|
||||||
unsigned NumValues = ValueVTs.size();
|
unsigned NumValues = ValueVTs.size();
|
||||||
if (NumValues == 0)
|
if (NumValues == 0)
|
||||||
return;
|
return;
|
||||||
@ -3390,7 +3393,7 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
|
|||||||
}
|
}
|
||||||
|
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
ComputeValueVTs(TLI, I.getType(), ValueVTs);
|
ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
|
||||||
|
|
||||||
if (HasChain)
|
if (HasChain)
|
||||||
ValueVTs.push_back(MVT::Other);
|
ValueVTs.push_back(MVT::Other);
|
||||||
@ -6653,7 +6656,7 @@ void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
|
|||||||
// Create the return types based on the intrinsic definition
|
// Create the return types based on the intrinsic definition
|
||||||
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
||||||
SmallVector<EVT, 3> ValueVTs;
|
SmallVector<EVT, 3> ValueVTs;
|
||||||
ComputeValueVTs(TLI, CS->getType(), ValueVTs);
|
ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
|
||||||
assert(ValueVTs.size() == 1 && "Expected only one return value type.");
|
assert(ValueVTs.size() == 1 && "Expected only one return value type.");
|
||||||
|
|
||||||
// There is always a chain and a glue type at the end
|
// There is always a chain and a glue type at the end
|
||||||
@ -6718,10 +6721,10 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
|
|||||||
SmallVector<EVT, 4> RetTys;
|
SmallVector<EVT, 4> RetTys;
|
||||||
SmallVector<uint64_t, 4> Offsets;
|
SmallVector<uint64_t, 4> Offsets;
|
||||||
auto &DL = CLI.DAG.getDataLayout();
|
auto &DL = CLI.DAG.getDataLayout();
|
||||||
ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
|
ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
|
||||||
|
|
||||||
SmallVector<ISD::OutputArg, 4> Outs;
|
SmallVector<ISD::OutputArg, 4> Outs;
|
||||||
GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
|
GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
|
||||||
|
|
||||||
bool CanLowerReturn =
|
bool CanLowerReturn =
|
||||||
this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
|
this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
|
||||||
@ -6784,7 +6787,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
|
|||||||
ArgListTy &Args = CLI.getArgs();
|
ArgListTy &Args = CLI.getArgs();
|
||||||
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
|
ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
|
||||||
Type *FinalType = Args[i].Ty;
|
Type *FinalType = Args[i].Ty;
|
||||||
if (Args[i].isByVal)
|
if (Args[i].isByVal)
|
||||||
FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
|
FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
|
||||||
@ -6923,7 +6926,7 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
|
|||||||
SmallVector<EVT, 1> PVTs;
|
SmallVector<EVT, 1> PVTs;
|
||||||
Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
|
Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
|
||||||
|
|
||||||
ComputeValueVTs(*this, PtrRetTy, PVTs);
|
ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
|
||||||
assert(PVTs.size() == 1 && "Pointers should fit in one register");
|
assert(PVTs.size() == 1 && "Pointers should fit in one register");
|
||||||
EVT PtrVT = PVTs[0];
|
EVT PtrVT = PVTs[0];
|
||||||
|
|
||||||
@ -6997,7 +7000,8 @@ SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
|
|||||||
assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
|
assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
|
||||||
|
|
||||||
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
||||||
RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
|
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
|
||||||
|
V->getType());
|
||||||
SDValue Chain = DAG.getEntryNode();
|
SDValue Chain = DAG.getEntryNode();
|
||||||
|
|
||||||
ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
|
ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
|
||||||
@ -7036,7 +7040,8 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
|
|||||||
if (!FuncInfo->CanLowerReturn) {
|
if (!FuncInfo->CanLowerReturn) {
|
||||||
// Put in an sret pointer parameter before all the other parameters.
|
// Put in an sret pointer parameter before all the other parameters.
|
||||||
SmallVector<EVT, 1> ValueVTs;
|
SmallVector<EVT, 1> ValueVTs;
|
||||||
ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
|
ComputeValueVTs(*TLI, DAG.getDataLayout(),
|
||||||
|
PointerType::getUnqual(F.getReturnType()), ValueVTs);
|
||||||
|
|
||||||
// NOTE: Assuming that a pointer will never break down to more than one VT
|
// NOTE: Assuming that a pointer will never break down to more than one VT
|
||||||
// or one register.
|
// or one register.
|
||||||
@ -7053,7 +7058,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
|
|||||||
for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
|
for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
|
||||||
I != E; ++I, ++Idx) {
|
I != E; ++I, ++Idx) {
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
ComputeValueVTs(*TLI, I->getType(), ValueVTs);
|
ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
|
||||||
bool isArgValueUsed = !I->use_empty();
|
bool isArgValueUsed = !I->use_empty();
|
||||||
unsigned PartBase = 0;
|
unsigned PartBase = 0;
|
||||||
Type *FinalType = I->getType();
|
Type *FinalType = I->getType();
|
||||||
@ -7153,7 +7158,8 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
|
|||||||
// Create a virtual register for the sret pointer, and put in a copy
|
// Create a virtual register for the sret pointer, and put in a copy
|
||||||
// from the sret argument into it.
|
// from the sret argument into it.
|
||||||
SmallVector<EVT, 1> ValueVTs;
|
SmallVector<EVT, 1> ValueVTs;
|
||||||
ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
|
ComputeValueVTs(*TLI, DAG.getDataLayout(),
|
||||||
|
PointerType::getUnqual(F.getReturnType()), ValueVTs);
|
||||||
MVT VT = ValueVTs[0].getSimpleVT();
|
MVT VT = ValueVTs[0].getSimpleVT();
|
||||||
MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
|
MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
|
||||||
ISD::NodeType AssertOp = ISD::DELETED_NODE;
|
ISD::NodeType AssertOp = ISD::DELETED_NODE;
|
||||||
@ -7177,7 +7183,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
|
|||||||
++I, ++Idx) {
|
++I, ++Idx) {
|
||||||
SmallVector<SDValue, 4> ArgValues;
|
SmallVector<SDValue, 4> ArgValues;
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
ComputeValueVTs(*TLI, I->getType(), ValueVTs);
|
ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
|
||||||
unsigned NumValues = ValueVTs.size();
|
unsigned NumValues = ValueVTs.size();
|
||||||
|
|
||||||
// If this argument is unused then remember its value. It is used to generate
|
// If this argument is unused then remember its value. It is used to generate
|
||||||
@ -7324,7 +7330,7 @@ SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
|
|||||||
// the input for this MBB.
|
// the input for this MBB.
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
|
||||||
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
|
ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
|
||||||
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
|
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
|
||||||
EVT VT = ValueVTs[vti];
|
EVT VT = ValueVTs[vti];
|
||||||
unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
|
unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
|
||||||
|
@ -915,8 +915,8 @@ struct RegsForValue {
|
|||||||
|
|
||||||
RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt);
|
RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt);
|
||||||
|
|
||||||
RegsForValue(LLVMContext &Context, const TargetLowering &tli, unsigned Reg,
|
RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
|
||||||
Type *Ty);
|
const DataLayout &DL, unsigned Reg, Type *Ty);
|
||||||
|
|
||||||
/// append - Add the specified values to this one.
|
/// append - Add the specified values to this one.
|
||||||
void append(const RegsForValue &RHS) {
|
void append(const RegsForValue &RHS) {
|
||||||
|
@ -337,9 +337,9 @@ lowerCallFromStatepoint(ImmutableStatepoint ISP, MachineBasicBlock *LandingPad,
|
|||||||
// TODO: To eliminate this problem we can remove gc.result intrinsics
|
// TODO: To eliminate this problem we can remove gc.result intrinsics
|
||||||
// completelly and make statepoint call to return a tuple.
|
// completelly and make statepoint call to return a tuple.
|
||||||
unsigned Reg = Builder.FuncInfo.CreateRegs(ISP.getActualReturnType());
|
unsigned Reg = Builder.FuncInfo.CreateRegs(ISP.getActualReturnType());
|
||||||
RegsForValue RFV(*Builder.DAG.getContext(),
|
RegsForValue RFV(
|
||||||
Builder.DAG.getTargetLoweringInfo(), Reg,
|
*Builder.DAG.getContext(), Builder.DAG.getTargetLoweringInfo(),
|
||||||
ISP.getActualReturnType());
|
Builder.DAG.getDataLayout(), Reg, ISP.getActualReturnType());
|
||||||
SDValue Chain = Builder.DAG.getEntryNode();
|
SDValue Chain = Builder.DAG.getEntryNode();
|
||||||
|
|
||||||
RFV.getCopyToRegs(ReturnValue, Builder.DAG, Builder.getCurSDLoc(), Chain,
|
RFV.getCopyToRegs(ReturnValue, Builder.DAG, Builder.getCurSDLoc(), Chain,
|
||||||
|
@ -1484,11 +1484,11 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT
|
|||||||
/// type of the given function. This does not require a DAG or a return value,
|
/// type of the given function. This does not require a DAG or a return value,
|
||||||
/// and is suitable for use before any DAGs for the function are constructed.
|
/// and is suitable for use before any DAGs for the function are constructed.
|
||||||
/// TODO: Move this out of TargetLowering.cpp.
|
/// TODO: Move this out of TargetLowering.cpp.
|
||||||
void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
|
void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr,
|
||||||
SmallVectorImpl<ISD::OutputArg> &Outs,
|
SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||||
const TargetLowering &TLI) {
|
const TargetLowering &TLI, const DataLayout &DL) {
|
||||||
SmallVector<EVT, 4> ValueVTs;
|
SmallVector<EVT, 4> ValueVTs;
|
||||||
ComputeValueVTs(TLI, ReturnType, ValueVTs);
|
ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
|
||||||
unsigned NumValues = ValueVTs.size();
|
unsigned NumValues = ValueVTs.size();
|
||||||
if (NumValues == 0) return;
|
if (NumValues == 0) return;
|
||||||
|
|
||||||
|
@ -3689,7 +3689,7 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
|
|||||||
if (Ret->getNumOperands() > 0) {
|
if (Ret->getNumOperands() > 0) {
|
||||||
CallingConv::ID CC = F.getCallingConv();
|
CallingConv::ID CC = F.getCallingConv();
|
||||||
SmallVector<ISD::OutputArg, 4> Outs;
|
SmallVector<ISD::OutputArg, 4> Outs;
|
||||||
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
|
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
|
||||||
|
|
||||||
// Analyze operands of the call, assigning locations to each operand.
|
// Analyze operands of the call, assigning locations to each operand.
|
||||||
SmallVector<CCValAssign, 16> ValLocs;
|
SmallVector<CCValAssign, 16> ValLocs;
|
||||||
|
@ -2093,7 +2093,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
|
|||||||
CallingConv::ID CC = F.getCallingConv();
|
CallingConv::ID CC = F.getCallingConv();
|
||||||
if (Ret->getNumOperands() > 0) {
|
if (Ret->getNumOperands() > 0) {
|
||||||
SmallVector<ISD::OutputArg, 4> Outs;
|
SmallVector<ISD::OutputArg, 4> Outs;
|
||||||
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
|
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
|
||||||
|
|
||||||
// Analyze operands of the call, assigning locations to each operand.
|
// Analyze operands of the call, assigning locations to each operand.
|
||||||
SmallVector<CCValAssign, 16> ValLocs;
|
SmallVector<CCValAssign, 16> ValLocs;
|
||||||
|
@ -1415,7 +1415,8 @@ bool MipsFastISel::selectRet(const Instruction *I) {
|
|||||||
if (Ret->getNumOperands() > 0) {
|
if (Ret->getNumOperands() > 0) {
|
||||||
CallingConv::ID CC = F.getCallingConv();
|
CallingConv::ID CC = F.getCallingConv();
|
||||||
SmallVector<ISD::OutputArg, 4> Outs;
|
SmallVector<ISD::OutputArg, 4> Outs;
|
||||||
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
|
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
|
||||||
|
|
||||||
// Analyze operands of the call, assigning locations to each operand.
|
// Analyze operands of the call, assigning locations to each operand.
|
||||||
SmallVector<CCValAssign, 16> ValLocs;
|
SmallVector<CCValAssign, 16> ValLocs;
|
||||||
MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
|
MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
|
||||||
|
@ -340,7 +340,7 @@ MCOperand NVPTXAsmPrinter::GetSymbolRef(const MCSymbol *Symbol) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
void NVPTXAsmPrinter::printReturnValStr(const Function *F, raw_ostream &O) {
|
void NVPTXAsmPrinter::printReturnValStr(const Function *F, raw_ostream &O) {
|
||||||
const DataLayout *TD = TM.getDataLayout();
|
const DataLayout &DL = getDataLayout();
|
||||||
const TargetLowering *TLI = nvptxSubtarget->getTargetLowering();
|
const TargetLowering *TLI = nvptxSubtarget->getTargetLowering();
|
||||||
|
|
||||||
Type *Ty = F->getReturnType();
|
Type *Ty = F->getReturnType();
|
||||||
@ -369,17 +369,17 @@ void NVPTXAsmPrinter::printReturnValStr(const Function *F, raw_ostream &O) {
|
|||||||
O << ".param .b" << TLI->getPointerTy().getSizeInBits()
|
O << ".param .b" << TLI->getPointerTy().getSizeInBits()
|
||||||
<< " func_retval0";
|
<< " func_retval0";
|
||||||
} else if ((Ty->getTypeID() == Type::StructTyID) || isa<VectorType>(Ty)) {
|
} else if ((Ty->getTypeID() == Type::StructTyID) || isa<VectorType>(Ty)) {
|
||||||
unsigned totalsz = TD->getTypeAllocSize(Ty);
|
unsigned totalsz = DL.getTypeAllocSize(Ty);
|
||||||
unsigned retAlignment = 0;
|
unsigned retAlignment = 0;
|
||||||
if (!llvm::getAlign(*F, 0, retAlignment))
|
if (!llvm::getAlign(*F, 0, retAlignment))
|
||||||
retAlignment = TD->getABITypeAlignment(Ty);
|
retAlignment = DL.getABITypeAlignment(Ty);
|
||||||
O << ".param .align " << retAlignment << " .b8 func_retval0[" << totalsz
|
O << ".param .align " << retAlignment << " .b8 func_retval0[" << totalsz
|
||||||
<< "]";
|
<< "]";
|
||||||
} else
|
} else
|
||||||
llvm_unreachable("Unknown return type");
|
llvm_unreachable("Unknown return type");
|
||||||
} else {
|
} else {
|
||||||
SmallVector<EVT, 16> vtparts;
|
SmallVector<EVT, 16> vtparts;
|
||||||
ComputeValueVTs(*TLI, Ty, vtparts);
|
ComputeValueVTs(*TLI, DL, Ty, vtparts);
|
||||||
unsigned idx = 0;
|
unsigned idx = 0;
|
||||||
for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
|
for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
|
||||||
unsigned elems = 1;
|
unsigned elems = 1;
|
||||||
@ -1579,7 +1579,7 @@ void NVPTXAsmPrinter::emitFunctionParamList(const Function *F, raw_ostream &O) {
|
|||||||
// Further, if a part is vector, print the above for
|
// Further, if a part is vector, print the above for
|
||||||
// each vector element.
|
// each vector element.
|
||||||
SmallVector<EVT, 16> vtparts;
|
SmallVector<EVT, 16> vtparts;
|
||||||
ComputeValueVTs(*TLI, ETy, vtparts);
|
ComputeValueVTs(*TLI, getDataLayout(), ETy, vtparts);
|
||||||
for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
|
for (unsigned i = 0, e = vtparts.size(); i != e; ++i) {
|
||||||
unsigned elems = 1;
|
unsigned elems = 1;
|
||||||
EVT elemtype = vtparts[i];
|
EVT elemtype = vtparts[i];
|
||||||
|
@ -80,14 +80,14 @@ static bool IsPTXVectorType(MVT VT) {
|
|||||||
/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
|
/// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
|
||||||
/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
|
/// same number of types as the Ins/Outs arrays in LowerFormalArguments,
|
||||||
/// LowerCall, and LowerReturn.
|
/// LowerCall, and LowerReturn.
|
||||||
static void ComputePTXValueVTs(const TargetLowering &TLI, Type *Ty,
|
static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
|
||||||
SmallVectorImpl<EVT> &ValueVTs,
|
Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
|
||||||
SmallVectorImpl<uint64_t> *Offsets = nullptr,
|
SmallVectorImpl<uint64_t> *Offsets = nullptr,
|
||||||
uint64_t StartingOffset = 0) {
|
uint64_t StartingOffset = 0) {
|
||||||
SmallVector<EVT, 16> TempVTs;
|
SmallVector<EVT, 16> TempVTs;
|
||||||
SmallVector<uint64_t, 16> TempOffsets;
|
SmallVector<uint64_t, 16> TempOffsets;
|
||||||
|
|
||||||
ComputeValueVTs(TLI, Ty, TempVTs, &TempOffsets, StartingOffset);
|
ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
|
||||||
for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
|
||||||
EVT VT = TempVTs[i];
|
EVT VT = TempVTs[i];
|
||||||
uint64_t Off = TempOffsets[i];
|
uint64_t Off = TempOffsets[i];
|
||||||
@ -960,7 +960,7 @@ NVPTXTargetLowering::getPrototype(Type *retTy, const ArgListTy &Args,
|
|||||||
O << "[" << sz << "]";
|
O << "[" << sz << "]";
|
||||||
// update the index for Outs
|
// update the index for Outs
|
||||||
SmallVector<EVT, 16> vtparts;
|
SmallVector<EVT, 16> vtparts;
|
||||||
ComputeValueVTs(*this, Ty, vtparts);
|
ComputeValueVTs(*this, *TD, Ty, vtparts);
|
||||||
if (unsigned len = vtparts.size())
|
if (unsigned len = vtparts.size())
|
||||||
OIdx += len - 1;
|
OIdx += len - 1;
|
||||||
continue;
|
continue;
|
||||||
@ -1064,9 +1064,9 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
assert(isABI && "Non-ABI compilation is not supported");
|
assert(isABI && "Non-ABI compilation is not supported");
|
||||||
if (!isABI)
|
if (!isABI)
|
||||||
return Chain;
|
return Chain;
|
||||||
const DataLayout *TD = getDataLayout();
|
|
||||||
MachineFunction &MF = DAG.getMachineFunction();
|
MachineFunction &MF = DAG.getMachineFunction();
|
||||||
const Function *F = MF.getFunction();
|
const Function *F = MF.getFunction();
|
||||||
|
auto &DL = MF.getDataLayout();
|
||||||
|
|
||||||
SDValue tempChain = Chain;
|
SDValue tempChain = Chain;
|
||||||
Chain = DAG.getCALLSEQ_START(Chain,
|
Chain = DAG.getCALLSEQ_START(Chain,
|
||||||
@ -1096,11 +1096,11 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
// aggregate
|
// aggregate
|
||||||
SmallVector<EVT, 16> vtparts;
|
SmallVector<EVT, 16> vtparts;
|
||||||
SmallVector<uint64_t, 16> Offsets;
|
SmallVector<uint64_t, 16> Offsets;
|
||||||
ComputePTXValueVTs(*this, Ty, vtparts, &Offsets, 0);
|
ComputePTXValueVTs(*this, DL, Ty, vtparts, &Offsets, 0);
|
||||||
|
|
||||||
unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
|
unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
|
||||||
// declare .param .align <align> .b8 .param<n>[<size>];
|
// declare .param .align <align> .b8 .param<n>[<size>];
|
||||||
unsigned sz = TD->getTypeAllocSize(Ty);
|
unsigned sz = DL.getTypeAllocSize(Ty);
|
||||||
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
|
SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
|
||||||
MVT::i32),
|
MVT::i32),
|
||||||
@ -1140,7 +1140,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
EVT ObjectVT = getValueType(Ty);
|
EVT ObjectVT = getValueType(Ty);
|
||||||
unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
|
unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
|
||||||
// declare .param .align <align> .b8 .param<n>[<size>];
|
// declare .param .align <align> .b8 .param<n>[<size>];
|
||||||
unsigned sz = TD->getTypeAllocSize(Ty);
|
unsigned sz = DL.getTypeAllocSize(Ty);
|
||||||
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||||
SDValue DeclareParamOps[] = { Chain,
|
SDValue DeclareParamOps[] = { Chain,
|
||||||
DAG.getConstant(align, dl, MVT::i32),
|
DAG.getConstant(align, dl, MVT::i32),
|
||||||
@ -1321,7 +1321,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
SmallVector<uint64_t, 16> Offsets;
|
SmallVector<uint64_t, 16> Offsets;
|
||||||
const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
|
const PointerType *PTy = dyn_cast<PointerType>(Args[i].Ty);
|
||||||
assert(PTy && "Type of a byval parameter should be pointer");
|
assert(PTy && "Type of a byval parameter should be pointer");
|
||||||
ComputePTXValueVTs(*this, PTy->getElementType(), vtparts, &Offsets, 0);
|
ComputePTXValueVTs(*this, DL, PTy->getElementType(), vtparts, &Offsets, 0);
|
||||||
|
|
||||||
// declare .param .align <align> .b8 .param<n>[<size>];
|
// declare .param .align <align> .b8 .param<n>[<size>];
|
||||||
unsigned sz = Outs[OIdx].Flags.getByValSize();
|
unsigned sz = Outs[OIdx].Flags.getByValSize();
|
||||||
@ -1371,12 +1371,12 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
// Handle Result
|
// Handle Result
|
||||||
if (Ins.size() > 0) {
|
if (Ins.size() > 0) {
|
||||||
SmallVector<EVT, 16> resvtparts;
|
SmallVector<EVT, 16> resvtparts;
|
||||||
ComputeValueVTs(*this, retTy, resvtparts);
|
ComputeValueVTs(*this, DL, retTy, resvtparts);
|
||||||
|
|
||||||
// Declare
|
// Declare
|
||||||
// .param .align 16 .b8 retval0[<size-in-bytes>], or
|
// .param .align 16 .b8 retval0[<size-in-bytes>], or
|
||||||
// .param .b<size-in-bits> retval0
|
// .param .b<size-in-bits> retval0
|
||||||
unsigned resultsz = TD->getTypeAllocSizeInBits(retTy);
|
unsigned resultsz = DL.getTypeAllocSizeInBits(retTy);
|
||||||
// Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
|
// Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
|
||||||
// these three types to match the logic in
|
// these three types to match the logic in
|
||||||
// NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
|
// NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
|
||||||
@ -1590,13 +1590,13 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
|
Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
|
||||||
InVals.push_back(Elt);
|
InVals.push_back(Elt);
|
||||||
}
|
}
|
||||||
Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
|
Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
SmallVector<EVT, 16> VTs;
|
SmallVector<EVT, 16> VTs;
|
||||||
SmallVector<uint64_t, 16> Offsets;
|
SmallVector<uint64_t, 16> Offsets;
|
||||||
ComputePTXValueVTs(*this, retTy, VTs, &Offsets, 0);
|
ComputePTXValueVTs(*this, DL, retTy, VTs, &Offsets, 0);
|
||||||
assert(VTs.size() == Ins.size() && "Bad value decomposition");
|
assert(VTs.size() == Ins.size() && "Bad value decomposition");
|
||||||
unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
|
unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
|
||||||
for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
|
for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
|
||||||
@ -1608,8 +1608,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
|||||||
|
|
||||||
SmallVector<EVT, 4> LoadRetVTs;
|
SmallVector<EVT, 4> LoadRetVTs;
|
||||||
EVT TheLoadType = VTs[i];
|
EVT TheLoadType = VTs[i];
|
||||||
if (retTy->isIntegerTy() &&
|
if (retTy->isIntegerTy() && DL.getTypeAllocSizeInBits(retTy) < 32) {
|
||||||
TD->getTypeAllocSizeInBits(retTy) < 32) {
|
|
||||||
// This is for integer types only, and specifically not for
|
// This is for integer types only, and specifically not for
|
||||||
// aggregates.
|
// aggregates.
|
||||||
LoadRetVTs.push_back(MVT::i32);
|
LoadRetVTs.push_back(MVT::i32);
|
||||||
@ -2064,7 +2063,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
|
const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
|
||||||
SmallVectorImpl<SDValue> &InVals) const {
|
SmallVectorImpl<SDValue> &InVals) const {
|
||||||
MachineFunction &MF = DAG.getMachineFunction();
|
MachineFunction &MF = DAG.getMachineFunction();
|
||||||
const DataLayout *TD = getDataLayout();
|
const DataLayout &DL = MF.getDataLayout();
|
||||||
|
|
||||||
const Function *F = MF.getFunction();
|
const Function *F = MF.getFunction();
|
||||||
const AttributeSet &PAL = F->getAttributes();
|
const AttributeSet &PAL = F->getAttributes();
|
||||||
@ -2118,7 +2117,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
if (Ty->isAggregateType()) {
|
if (Ty->isAggregateType()) {
|
||||||
SmallVector<EVT, 16> vtparts;
|
SmallVector<EVT, 16> vtparts;
|
||||||
|
|
||||||
ComputePTXValueVTs(*this, Ty, vtparts);
|
ComputePTXValueVTs(*this, DL, Ty, vtparts);
|
||||||
assert(vtparts.size() > 0 && "empty aggregate type not expected");
|
assert(vtparts.size() > 0 && "empty aggregate type not expected");
|
||||||
for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
|
for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
|
||||||
++parti) {
|
++parti) {
|
||||||
@ -2156,7 +2155,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
// NOTE: Here, we lose the ability to issue vector loads for vectors
|
// NOTE: Here, we lose the ability to issue vector loads for vectors
|
||||||
// that are a part of a struct. This should be investigated in the
|
// that are a part of a struct. This should be investigated in the
|
||||||
// future.
|
// future.
|
||||||
ComputePTXValueVTs(*this, Ty, vtparts, &offsets, 0);
|
ComputePTXValueVTs(*this, DL, Ty, vtparts, &offsets, 0);
|
||||||
assert(vtparts.size() > 0 && "empty aggregate type not expected");
|
assert(vtparts.size() > 0 && "empty aggregate type not expected");
|
||||||
bool aggregateIsPacked = false;
|
bool aggregateIsPacked = false;
|
||||||
if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
|
if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
|
||||||
@ -2172,10 +2171,10 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
SDValue srcAddr =
|
SDValue srcAddr =
|
||||||
DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
|
DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg,
|
||||||
DAG.getConstant(offsets[parti], dl, getPointerTy()));
|
DAG.getConstant(offsets[parti], dl, getPointerTy()));
|
||||||
unsigned partAlign =
|
unsigned partAlign = aggregateIsPacked
|
||||||
aggregateIsPacked ? 1
|
? 1
|
||||||
: TD->getABITypeAlignment(
|
: DL.getABITypeAlignment(
|
||||||
partVT.getTypeForEVT(F->getContext()));
|
partVT.getTypeForEVT(F->getContext()));
|
||||||
SDValue p;
|
SDValue p;
|
||||||
if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
|
if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
|
||||||
ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
|
ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
|
||||||
@ -2212,9 +2211,9 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
Value *SrcValue = Constant::getNullValue(PointerType::get(
|
Value *SrcValue = Constant::getNullValue(PointerType::get(
|
||||||
EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
|
EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
|
||||||
SDValue P = DAG.getLoad(
|
SDValue P = DAG.getLoad(
|
||||||
EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
|
EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
|
||||||
false, true,
|
true,
|
||||||
TD->getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
|
DL.getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
|
||||||
if (P.getNode())
|
if (P.getNode())
|
||||||
P.getNode()->setIROrder(idx + 1);
|
P.getNode()->setIROrder(idx + 1);
|
||||||
|
|
||||||
@ -2229,9 +2228,9 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
Value *SrcValue = Constant::getNullValue(PointerType::get(
|
Value *SrcValue = Constant::getNullValue(PointerType::get(
|
||||||
VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
|
VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
|
||||||
SDValue P = DAG.getLoad(
|
SDValue P = DAG.getLoad(
|
||||||
VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false,
|
VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
|
||||||
false, true,
|
true,
|
||||||
TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
|
DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
|
||||||
if (P.getNode())
|
if (P.getNode())
|
||||||
P.getNode()->setIROrder(idx + 1);
|
P.getNode()->setIROrder(idx + 1);
|
||||||
|
|
||||||
@ -2275,7 +2274,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
SDValue P = DAG.getLoad(
|
SDValue P = DAG.getLoad(
|
||||||
VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
|
VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
|
||||||
false, true,
|
false, true,
|
||||||
TD->getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
|
DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
|
||||||
if (P.getNode())
|
if (P.getNode())
|
||||||
P.getNode()->setIROrder(idx + 1);
|
P.getNode()->setIROrder(idx + 1);
|
||||||
|
|
||||||
@ -2288,7 +2287,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
|
Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
|
||||||
InVals.push_back(Elt);
|
InVals.push_back(Elt);
|
||||||
}
|
}
|
||||||
Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
|
Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
|
||||||
}
|
}
|
||||||
InsIdx += NumElts;
|
InsIdx += NumElts;
|
||||||
}
|
}
|
||||||
@ -2307,14 +2306,15 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
|
|||||||
if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
|
if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
|
||||||
ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
|
ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
|
||||||
ISD::SEXTLOAD : ISD::ZEXTLOAD;
|
ISD::SEXTLOAD : ISD::ZEXTLOAD;
|
||||||
p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
|
p = DAG.getExtLoad(
|
||||||
MachinePointerInfo(srcValue), ObjectVT, false, false,
|
ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue),
|
||||||
false,
|
ObjectVT, false, false, false,
|
||||||
TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
|
DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
|
||||||
} else {
|
} else {
|
||||||
p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
|
p = DAG.getLoad(
|
||||||
MachinePointerInfo(srcValue), false, false, false,
|
Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue), false,
|
||||||
TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
|
false, false,
|
||||||
|
DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
|
||||||
}
|
}
|
||||||
if (p.getNode())
|
if (p.getNode())
|
||||||
p.getNode()->setIROrder(idx + 1);
|
p.getNode()->setIROrder(idx + 1);
|
||||||
@ -2493,7 +2493,7 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
|
|||||||
} else {
|
} else {
|
||||||
SmallVector<EVT, 16> ValVTs;
|
SmallVector<EVT, 16> ValVTs;
|
||||||
SmallVector<uint64_t, 16> Offsets;
|
SmallVector<uint64_t, 16> Offsets;
|
||||||
ComputePTXValueVTs(*this, RetTy, ValVTs, &Offsets, 0);
|
ComputePTXValueVTs(*this, DAG.getDataLayout(), RetTy, ValVTs, &Offsets, 0);
|
||||||
assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
|
assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
|
||||||
|
|
||||||
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
|
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
|
||||||
|
@ -1594,7 +1594,7 @@ bool PPCFastISel::SelectRet(const Instruction *I) {
|
|||||||
|
|
||||||
if (Ret->getNumOperands() > 0) {
|
if (Ret->getNumOperands() > 0) {
|
||||||
SmallVector<ISD::OutputArg, 4> Outs;
|
SmallVector<ISD::OutputArg, 4> Outs;
|
||||||
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
|
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
|
||||||
|
|
||||||
// Analyze operands of the call, assigning locations to each operand.
|
// Analyze operands of the call, assigning locations to each operand.
|
||||||
SmallVector<CCValAssign, 16> ValLocs;
|
SmallVector<CCValAssign, 16> ValLocs;
|
||||||
|
@ -1000,7 +1000,8 @@ bool X86FastISel::X86SelectRet(const Instruction *I) {
|
|||||||
|
|
||||||
if (Ret->getNumOperands() > 0) {
|
if (Ret->getNumOperands() > 0) {
|
||||||
SmallVector<ISD::OutputArg, 4> Outs;
|
SmallVector<ISD::OutputArg, 4> Outs;
|
||||||
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
|
GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI,
|
||||||
|
MF->getDataLayout());
|
||||||
|
|
||||||
// Analyze operands of the call, assigning locations to each operand.
|
// Analyze operands of the call, assigning locations to each operand.
|
||||||
SmallVector<CCValAssign, 16> ValLocs;
|
SmallVector<CCValAssign, 16> ValLocs;
|
||||||
|
Loading…
Reference in New Issue
Block a user