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ARM::tPOP and tPOP_RET each has an extra writeback operand now.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83214 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-10-01 20:54:53 +00:00
parent 95923d70d9
commit 10469f8e48
4 changed files with 19 additions and 2 deletions
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6
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -1359,9 +1359,11 @@ bool ARMConstantIslands::UndoLRSpillRestore() {
bool MadeChange = false; bool MadeChange = false;
for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) { for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
MachineInstr *MI = PushPopMIs[i]; MachineInstr *MI = PushPopMIs[i];
// First two operands are predicates, the third is a zero since there
// is no writeback.
if (MI->getOpcode() == ARM::tPOP_RET && if (MI->getOpcode() == ARM::tPOP_RET &&
MI->getOperand(2).getReg() == ARM::PC && MI->getOperand(3).getReg() == ARM::PC &&
MI->getNumExplicitOperands() == 3) { MI->getNumExplicitOperands() == 4) {
BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET)); BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
MI->eraseFromParent(); MI->eraseFromParent();
MadeChange = true; MadeChange = true;

1
lib/Target/ARM/Thumb1InstrInfo.cpp
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@ -178,6 +178,7 @@ restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP)); MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
AddDefaultPred(MIB); AddDefaultPred(MIB);
MIB.addReg(0); // No write back.
bool NumRegs = 0; bool NumRegs = 0;
for (unsigned i = CSI.size(); i != 0; --i) { for (unsigned i = CSI.size(); i != 0; --i) {

1
lib/Target/ARM/Thumb1RegisterInfo.cpp
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@ -863,6 +863,7 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF,
// Epilogue for vararg functions: pop LR to R3 and branch off it. // Epilogue for vararg functions: pop LR to R3 and branch off it.
// FIXME: Verify this is still ok when R3 is no longer being reserved. // FIXME: Verify this is still ok when R3 is no longer being reserved.
AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP)))
.addReg(0) // No write back.
.addReg(ARM::R3, RegState::Define); .addReg(ARM::R3, RegState::Define);
emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize); emitSPUpdate(MBB, MBBI, TII, dl, *this, VARegSaveSize);

13
test/CodeGen/Thumb/pop.ll Normal file
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@ -0,0 +1,13 @@
; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s
; rdar://7268481
define arm_apcscc void @t(i8* %a, ...) nounwind {
; CHECK: t:
; CHECK: pop {r3}
; CHECK-NEXT: add sp, #3 * 4
; CHECK-NEXT: bx r3
entry:
%a.addr = alloca i8*
store i8* %a, i8** %a.addr
ret void
}