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Don't produce ADDC/ADDE when expanding SHL unless they are legal

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for the target. This fixes PR3080.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59450 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2008-11-17 17:34:31 +00:00
parent 35fde15059
commit 104de6cf7b
2 changed files with 8 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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@ -1073,7 +1073,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
} else if (Amt == NVTBits) { } else if (Amt == NVTBits) {
Lo = DAG.getConstant(0, NVT); Lo = DAG.getConstant(0, NVT);
Hi = InL; Hi = InL;
} else if (Amt == 1) { } else if (Amt == 1 &&
TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) {
// Emit this X << 1 as X+X. // Emit this X << 1 as X+X.
SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
SDValue LoOps[2] = { InL, InL }; SDValue LoOps[2] = { InL, InL };

6
test/CodeGen/XCore/2008-11-17-Shl64.ll Normal file
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@ -0,0 +1,6 @@
; RUN: llvm-as < %s | llc -march=xcore > %t1.s
; PR3080
define i64 @test(i64 %a) {
%result = shl i64 %a, 1
ret i64 %result
}