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V8 never used the instrselectorgenerator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15791 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -16,7 +16,7 @@ TDFILE := $(SourceDir)/SparcV8.td
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# Make sure that tblgen is run, first thing.
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
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SparcV8GenInstrInfo.inc
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SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
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SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building SparcV8.td register names with tblgen"
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@echo "Building SparcV8.td register names with tblgen"
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@ -38,9 +38,5 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building SparcV8.td instruction information with tblgen"
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@echo "Building SparcV8.td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
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SparcV8GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building SparcV8.td instruction selector with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-selector -o $@
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clean::
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clean::
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$(VERB) rm -f *.inc
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$(VERB) rm -f *.inc
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@ -16,7 +16,7 @@ TDFILE := $(SourceDir)/SparcV8.td
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# Make sure that tblgen is run, first thing.
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
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SparcV8GenInstrInfo.inc
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SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
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SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building SparcV8.td register names with tblgen"
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@echo "Building SparcV8.td register names with tblgen"
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@ -38,9 +38,5 @@ SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building SparcV8.td instruction information with tblgen"
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@echo "Building SparcV8.td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
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SparcV8GenInstrSelector.inc:: $(TDFILES) $(TBLGEN)
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@echo "Building SparcV8.td instruction selector with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-selector -o $@
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clean::
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clean::
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$(VERB) rm -f *.inc
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$(VERB) rm -f *.inc
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