From 107f54a0026cfc455252c5a79b4860ace4bbbfc1 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Fri, 3 Aug 2007 00:17:42 +0000
Subject: [PATCH] add an observation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40772 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/README.txt | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt
index d70e90a3ca1..4648630c974 100644
--- a/lib/Target/X86/README.txt
+++ b/lib/Target/X86/README.txt
@@ -1103,3 +1103,30 @@ These instructions should go away:
 movaps %xmm1, 192(%esp) 
 movaps %xmm1, 224(%esp) 
 movaps %xmm1, 176(%esp)
+
+//===---------------------------------------------------------------------===//
+
+This is a "commutable two-address" register coallescing deficiency:
+
+define <4 x float> @test1(<4 x float> %V) {
+entry:
+        %tmp8 = shufflevector <4 x float> %V, <4 x float> undef, <4 x i32> < i32 3, i32 2, i32 1, i32 0 >               ; <<4 x float>> [#uses=1]
+        %add = add <4 x float> %tmp8, %V                ; <<4 x float>> [#uses=1]
+        ret <4 x float> %add
+}
+
+this codegens to:
+
+_test1:
+        pshufd  $27, %xmm0, %xmm1
+        addps   %xmm0, %xmm1
+        movaps  %xmm1, %xmm0
+        ret
+
+instead of:
+
+_test1:
+        pshufd  $27, %xmm0, %xmm1
+        addps   %xmm1, %xmm0
+        ret
+