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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-28 06:32:09 +00:00
ARM refactor am6offset usage for VLD1.
Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
0135fe1854
commit
10b90a9bbf
@ -2401,10 +2401,14 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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case ARM::VLD1q16:
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case ARM::VLD1q32:
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case ARM::VLD1q64:
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case ARM::VLD1q8_UPD:
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case ARM::VLD1q16_UPD:
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case ARM::VLD1q32_UPD:
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case ARM::VLD1q64_UPD:
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case ARM::VLD1q8wb_fixed:
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case ARM::VLD1q16wb_fixed:
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case ARM::VLD1q32wb_fixed:
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case ARM::VLD1q64wb_fixed:
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case ARM::VLD1q8wb_register:
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case ARM::VLD1q16wb_register:
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case ARM::VLD1q32wb_register:
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case ARM::VLD1q64wb_register:
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case ARM::VLD2d8:
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case ARM::VLD2d16:
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case ARM::VLD2d32:
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@ -2562,10 +2566,14 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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case ARM::VLD1q16Pseudo:
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case ARM::VLD1q32Pseudo:
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case ARM::VLD1q64Pseudo:
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case ARM::VLD1q8Pseudo_UPD:
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case ARM::VLD1q16Pseudo_UPD:
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case ARM::VLD1q32Pseudo_UPD:
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case ARM::VLD1q64Pseudo_UPD:
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case ARM::VLD1q8PseudoWB_register:
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case ARM::VLD1q16PseudoWB_register:
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case ARM::VLD1q32PseudoWB_register:
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case ARM::VLD1q64PseudoWB_register:
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case ARM::VLD1q8PseudoWB_fixed:
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case ARM::VLD1q16PseudoWB_fixed:
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case ARM::VLD1q32PseudoWB_fixed:
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case ARM::VLD1q64PseudoWB_fixed:
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case ARM::VLD2d8Pseudo:
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case ARM::VLD2d16Pseudo:
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case ARM::VLD2d32Pseudo:
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@ -102,7 +102,7 @@ namespace {
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unsigned PseudoOpc;
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unsigned RealOpc;
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bool IsLoad;
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bool HasWriteBack;
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bool HasWritebackOperand;
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NEONRegSpacing RegSpacing;
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unsigned char NumRegs; // D registers loaded or stored
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unsigned char RegElts; // elements per D register; used for lane ops
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@ -148,13 +148,17 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
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{ ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 ,false},
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{ ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 ,false},
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{ ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 ,false},
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{ ARM::VLD1q16PseudoWB_fixed, ARM::VLD1q16wb_fixed,true,false,SingleSpc, 2, 4 ,false},
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{ ARM::VLD1q16PseudoWB_register, ARM::VLD1q16wb_register, true, true, SingleSpc, 2, 4 ,false},
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{ ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 ,false},
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{ ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 ,false},
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{ ARM::VLD1q32PseudoWB_fixed, ARM::VLD1q32wb_fixed,true,false,SingleSpc, 2, 2 ,false},
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{ ARM::VLD1q32PseudoWB_register, ARM::VLD1q32wb_register, true, true, SingleSpc, 2, 2 ,false},
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{ ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 ,false},
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{ ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 ,false},
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{ ARM::VLD1q64PseudoWB_fixed, ARM::VLD1q64wb_fixed,true,false,SingleSpc, 2, 2 ,false},
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{ ARM::VLD1q64PseudoWB_register, ARM::VLD1q64wb_register, true, true, SingleSpc, 2, 1 ,false},
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{ ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 ,false},
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{ ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 ,false},
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{ ARM::VLD1q8PseudoWB_fixed, ARM::VLD1q8wb_fixed,true,false, SingleSpc, 2, 8 ,false},
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{ ARM::VLD1q8PseudoWB_register, ARM::VLD1q8wb_register,true,true,SingleSpc,2,8,false},
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{ ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4,true},
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{ ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4,true},
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@ -436,14 +440,14 @@ void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
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if (NumRegs > 3 && TableEntry->copyAllListRegs)
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MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
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if (TableEntry->HasWriteBack)
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if (TableEntry->HasWritebackOperand)
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MIB.addOperand(MI.getOperand(OpIdx++));
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// Copy the addrmode6 operands.
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MIB.addOperand(MI.getOperand(OpIdx++));
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MIB.addOperand(MI.getOperand(OpIdx++));
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// Copy the am6offset operand.
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if (TableEntry->HasWriteBack)
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if (TableEntry->HasWritebackOperand)
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MIB.addOperand(MI.getOperand(OpIdx++));
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// For an instruction writing double-spaced subregs, the pseudo instruction
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@ -488,14 +492,14 @@ void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
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TII->get(TableEntry->RealOpc));
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unsigned OpIdx = 0;
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if (TableEntry->HasWriteBack)
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if (TableEntry->HasWritebackOperand)
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MIB.addOperand(MI.getOperand(OpIdx++));
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// Copy the addrmode6 operands.
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MIB.addOperand(MI.getOperand(OpIdx++));
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MIB.addOperand(MI.getOperand(OpIdx++));
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// Copy the am6offset operand.
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if (TableEntry->HasWriteBack)
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if (TableEntry->HasWritebackOperand)
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MIB.addOperand(MI.getOperand(OpIdx++));
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bool SrcIsKill = MI.getOperand(OpIdx).isKill();
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@ -565,14 +569,14 @@ void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
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MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
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}
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if (TableEntry->HasWriteBack)
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if (TableEntry->HasWritebackOperand)
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MIB.addOperand(MI.getOperand(OpIdx++));
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// Copy the addrmode6 operands.
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MIB.addOperand(MI.getOperand(OpIdx++));
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MIB.addOperand(MI.getOperand(OpIdx++));
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// Copy the am6offset operand.
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if (TableEntry->HasWriteBack)
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if (TableEntry->HasWritebackOperand)
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MIB.addOperand(MI.getOperand(OpIdx++));
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// Grab the super-register source.
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@ -1068,10 +1072,14 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
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case ARM::VLD1q16Pseudo:
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case ARM::VLD1q32Pseudo:
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case ARM::VLD1q64Pseudo:
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case ARM::VLD1q8Pseudo_UPD:
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case ARM::VLD1q16Pseudo_UPD:
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case ARM::VLD1q32Pseudo_UPD:
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case ARM::VLD1q64Pseudo_UPD:
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case ARM::VLD1q8PseudoWB_register:
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case ARM::VLD1q16PseudoWB_register:
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case ARM::VLD1q32PseudoWB_register:
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case ARM::VLD1q64PseudoWB_register:
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case ARM::VLD1q8PseudoWB_fixed:
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case ARM::VLD1q16PseudoWB_fixed:
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case ARM::VLD1q32PseudoWB_fixed:
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case ARM::VLD1q64PseudoWB_fixed:
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case ARM::VLD2d8Pseudo:
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case ARM::VLD2d16Pseudo:
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case ARM::VLD2d32Pseudo:
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@ -1549,6 +1549,23 @@ SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
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return CurDAG->getTargetConstant(Alignment, MVT::i32);
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}
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// Get the register stride update opcode of a VLD/VST instruction that
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// is otherwise equivalent to the given fixed stride updating instruction.
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static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
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switch (Opc) {
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default: break;
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case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
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case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
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case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
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case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
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case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
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case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
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case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
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case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
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}
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return Opc; // If not one we handle, return it unchanged.
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}
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SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
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unsigned *DOpcodes, unsigned *QOpcodes0,
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unsigned *QOpcodes1) {
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@ -1612,7 +1629,14 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
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Ops.push_back(Align);
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if (isUpdating) {
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SDValue Inc = N->getOperand(AddrOpIdx + 1);
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Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
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// FIXME: VLD1 fixed increment doesn't need Reg0. Remove the reg0
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// case entirely when the rest are updated to that form, too.
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// Do that before committing this change. Likewise, the opcode
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// update call will become unconditional.
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if (NumVecs == 1 && !isa<ConstantSDNode>(Inc.getNode()))
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Opc = getVLDSTRegisterUpdateOpcode(Opc);
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if (NumVecs != 1 || !isa<ConstantSDNode>(Inc.getNode()))
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Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
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}
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Ops.push_back(Pred);
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Ops.push_back(Reg0);
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@ -2750,16 +2774,18 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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}
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case ARMISD::VLD1_UPD: {
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unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
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ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
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unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
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ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
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unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
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ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
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unsigned QOpcodes[] = { ARM::VLD1q8PseudoWB_fixed,
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ARM::VLD1q16PseudoWB_fixed,
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ARM::VLD1q32PseudoWB_fixed,
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ARM::VLD1q64PseudoWB_fixed };
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return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
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}
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case ARMISD::VLD2_UPD: {
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unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
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ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
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ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
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unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
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ARM::VLD2q32Pseudo_UPD };
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return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
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@ -2767,7 +2793,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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case ARMISD::VLD3_UPD: {
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unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
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ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
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ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
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unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
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ARM::VLD3q16Pseudo_UPD,
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ARM::VLD3q32Pseudo_UPD };
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@ -2779,7 +2805,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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case ARMISD::VLD4_UPD: {
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unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
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ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
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ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
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unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
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ARM::VLD4q16Pseudo_UPD,
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ARM::VLD4q32Pseudo_UPD };
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@ -259,6 +259,14 @@ class VLDQWBPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, am6offset:$offset), itin,
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"$addr.addr = $wb">;
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class VLDQWBfixedPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
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(ins addrmode6:$addr), itin,
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"$addr.addr = $wb">;
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class VLDQWBregisterPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
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(ins addrmode6:$addr, rGPR:$offset), itin,
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"$addr.addr = $wb">;
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class VLDQQPseudo<InstrItinClass itin>
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: PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
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class VLDQQWBPseudo<InstrItinClass itin>
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@ -309,37 +317,58 @@ def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
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def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
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// ...with address register writeback:
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class VLD1DWB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
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"vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDInstruction";
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multiclass VLD1DWB<bits<4> op7_4, string Dt> {
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def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn), IIC_VLD1u,
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"vld1", Dt, "$Vd, $Rn!",
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"$Rn.addr = $wb", []> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDInstruction";
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}
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def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
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"vld1", Dt, "$Vd, $Rn, $Rm",
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDInstruction";
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}
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}
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class VLD1QWB<bits<4> op7_4, string Dt>
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: NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
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"vld1", Dt, "$Vd, $Rn$Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDInstruction";
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multiclass VLD1QWB<bits<4> op7_4, string Dt> {
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def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn), IIC_VLD1x2u,
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"vld1", Dt, "$Vd, $Rn!",
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"$Rn.addr = $wb", []> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDInstruction";
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}
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def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
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"vld1", Dt, "$Vd, $Rn, $Rm",
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDInstruction";
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}
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}
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def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
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def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
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def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
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def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
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defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
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defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
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defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
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defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
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defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
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defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
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defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
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defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
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def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
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def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
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def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
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def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
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def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
|
||||
def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
|
||||
|
||||
// ...with 3 registers
|
||||
class VLD1D3<bits<4> op7_4, string Dt>
|
||||
|
||||
@ -2054,14 +2054,22 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
|
||||
|
||||
// Writeback operand
|
||||
switch (Inst.getOpcode()) {
|
||||
case ARM::VLD1d8_UPD:
|
||||
case ARM::VLD1d16_UPD:
|
||||
case ARM::VLD1d32_UPD:
|
||||
case ARM::VLD1d64_UPD:
|
||||
case ARM::VLD1q8_UPD:
|
||||
case ARM::VLD1q16_UPD:
|
||||
case ARM::VLD1q32_UPD:
|
||||
case ARM::VLD1q64_UPD:
|
||||
case ARM::VLD1d8wb_fixed:
|
||||
case ARM::VLD1d16wb_fixed:
|
||||
case ARM::VLD1d32wb_fixed:
|
||||
case ARM::VLD1d64wb_fixed:
|
||||
case ARM::VLD1d8wb_register:
|
||||
case ARM::VLD1d16wb_register:
|
||||
case ARM::VLD1d32wb_register:
|
||||
case ARM::VLD1d64wb_register:
|
||||
case ARM::VLD1q8wb_fixed:
|
||||
case ARM::VLD1q16wb_fixed:
|
||||
case ARM::VLD1q32wb_fixed:
|
||||
case ARM::VLD1q64wb_fixed:
|
||||
case ARM::VLD1q8wb_register:
|
||||
case ARM::VLD1q16wb_register:
|
||||
case ARM::VLD1q32wb_register:
|
||||
case ARM::VLD1q64wb_register:
|
||||
case ARM::VLD1d8T_UPD:
|
||||
case ARM::VLD1d16T_UPD:
|
||||
case ARM::VLD1d32T_UPD:
|
||||
@ -2103,11 +2111,42 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
|
||||
return MCDisassembler::Fail;
|
||||
|
||||
// AddrMode6 Offset (register)
|
||||
if (Rm == 0xD)
|
||||
Inst.addOperand(MCOperand::CreateReg(0));
|
||||
else if (Rm != 0xF) {
|
||||
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
|
||||
switch (Inst.getOpcode()) {
|
||||
default:
|
||||
// The below have been updated to have explicit am6offset split
|
||||
// between fixed and register offset. For those instructions not
|
||||
// yet updated, we need to add an additional reg0 operand for the
|
||||
// fixed variant.
|
||||
//
|
||||
// The fixed offset encodes as Rm == 0xd, so we check for that.
|
||||
if (Rm == 0xd) {
|
||||
Inst.addOperand(MCOperand::CreateReg(0));
|
||||
break;
|
||||
}
|
||||
// Fall through to handle the register offset variant.
|
||||
case ARM::VLD1d8wb_fixed:
|
||||
case ARM::VLD1d16wb_fixed:
|
||||
case ARM::VLD1d32wb_fixed:
|
||||
case ARM::VLD1d64wb_fixed:
|
||||
case ARM::VLD1d8wb_register:
|
||||
case ARM::VLD1d16wb_register:
|
||||
case ARM::VLD1d32wb_register:
|
||||
case ARM::VLD1d64wb_register:
|
||||
case ARM::VLD1q8wb_fixed:
|
||||
case ARM::VLD1q16wb_fixed:
|
||||
case ARM::VLD1q32wb_fixed:
|
||||
case ARM::VLD1q64wb_fixed:
|
||||
case ARM::VLD1q8wb_register:
|
||||
case ARM::VLD1q16wb_register:
|
||||
case ARM::VLD1q32wb_register:
|
||||
case ARM::VLD1q64wb_register:
|
||||
// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
|
||||
// variant encodes Rm == 0xf. Anything else is a register offset post-
|
||||
// increment and we need to add the register operand to the instruction.
|
||||
if (Rm != 0xD && Rm != 0xF &&
|
||||
!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
|
||||
return MCDisassembler::Fail;
|
||||
break;
|
||||
}
|
||||
|
||||
return S;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user