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Add FP +,-,*,/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24801 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -520,33 +520,41 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
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// Floating-point Add and Subtract Instructions, p. 146
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def FADDS : F3_3<2, 0b110100, 0b001000001,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fadds $src1, $src2, $dst", []>;
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"fadds $src1, $src2, $dst",
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[(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
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def FADDD : F3_3<2, 0b110100, 0b001000010,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"faddd $src1, $src2, $dst", []>;
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"faddd $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
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def FSUBS : F3_3<2, 0b110100, 0b001000101,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fsubs $src1, $src2, $dst", []>;
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"fsubs $src1, $src2, $dst",
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[(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
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def FSUBD : F3_3<2, 0b110100, 0b001000110,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fsubd $src1, $src2, $dst", []>;
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"fsubd $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
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// Floating-point Multiply and Divide Instructions, p. 147
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def FMULS : F3_3<2, 0b110100, 0b001001001,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fmuls $src1, $src2, $dst", []>;
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"fmuls $src1, $src2, $dst",
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[(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
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def FMULD : F3_3<2, 0b110100, 0b001001010,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fmuld $src1, $src2, $dst", []>;
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"fmuld $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
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def FSMULD : F3_3<2, 0b110100, 0b001101001,
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(ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fsmuld $src1, $src2, $dst", []>;
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def FDIVS : F3_3<2, 0b110100, 0b001001101,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fdivs $src1, $src2, $dst", []>;
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"fdivs $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
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def FDIVD : F3_3<2, 0b110100, 0b001001110,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fdivd $src1, $src2, $dst", []>;
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"fdivd $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
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// Floating-point Compare Instructions, p. 148
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// Note: the 2nd template arg is different for these guys.
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@ -520,33 +520,41 @@ def FABSS : F3_3<2, 0b110100, 0b000001001,
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// Floating-point Add and Subtract Instructions, p. 146
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def FADDS : F3_3<2, 0b110100, 0b001000001,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fadds $src1, $src2, $dst", []>;
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"fadds $src1, $src2, $dst",
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[(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
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def FADDD : F3_3<2, 0b110100, 0b001000010,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"faddd $src1, $src2, $dst", []>;
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"faddd $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
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def FSUBS : F3_3<2, 0b110100, 0b001000101,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fsubs $src1, $src2, $dst", []>;
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"fsubs $src1, $src2, $dst",
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[(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
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def FSUBD : F3_3<2, 0b110100, 0b001000110,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fsubd $src1, $src2, $dst", []>;
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"fsubd $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
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// Floating-point Multiply and Divide Instructions, p. 147
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def FMULS : F3_3<2, 0b110100, 0b001001001,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fmuls $src1, $src2, $dst", []>;
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"fmuls $src1, $src2, $dst",
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[(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
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def FMULD : F3_3<2, 0b110100, 0b001001010,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fmuld $src1, $src2, $dst", []>;
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"fmuld $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
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def FSMULD : F3_3<2, 0b110100, 0b001101001,
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(ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fsmuld $src1, $src2, $dst", []>;
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def FDIVS : F3_3<2, 0b110100, 0b001001101,
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(ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
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"fdivs $src1, $src2, $dst", []>;
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"fdivs $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
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def FDIVD : F3_3<2, 0b110100, 0b001001110,
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(ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
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"fdivd $src1, $src2, $dst", []>;
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"fdivd $src1, $src2, $dst",
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[(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
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// Floating-point Compare Instructions, p. 148
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// Note: the 2nd template arg is different for these guys.
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