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AVX-512: Scalar ERI intrinsics
including SAE mode and memory operand. Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future. The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect. I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction. http://reviews.llvm.org/D6378 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222820 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
e98441590b
commit
10c8f38047
@ -16799,6 +16799,23 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
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return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
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}
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static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
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SDValue PreservedSrc,
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const X86Subtarget *Subtarget,
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SelectionDAG &DAG) {
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if (isAllOnes(Mask))
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return Op;
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EVT VT = Op.getValueType();
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SDLoc dl(Op);
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// The mask should be of type MVT::i1
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SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
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if (PreservedSrc.getOpcode() == ISD::UNDEF)
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PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
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return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
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}
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static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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@ -16872,6 +16889,16 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
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RoundingMode),
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Mask, Src0, Subtarget, DAG);
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}
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case INTR_TYPE_SCALAR_MASK_RM: {
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SDValue Src1 = Op.getOperand(1);
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SDValue Src2 = Op.getOperand(2);
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SDValue Src0 = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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SDValue RoundingMode = Op.getOperand(5);
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
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RoundingMode),
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Mask, Src0, Subtarget, DAG);
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}
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case INTR_TYPE_2OP_MASK: {
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return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
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Op.getOperand(2)),
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@ -23,7 +23,11 @@ class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
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// Suffix used in the instruction mnemonic.
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string Suffix = suffix;
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string VTName = "v" # NumElts # EltVT;
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int NumEltsInVT = !if (!eq (NumElts, 1),
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!if (!eq (EltVT.Size, 32), 4,
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!if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts);
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string VTName = "v" # NumEltsInVT # EltVT;
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// The vector VT.
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ValueType VT = !cast<ValueType>(VTName);
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@ -57,9 +61,11 @@ class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
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// case of i64 element types for sub-512 integer vectors. For now, keep
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// MemOpFrag undefined in these cases.
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PatFrag MemOpFrag =
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!if (!eq (NumElts#EltTypeName, "1f32"), !cast<PatFrag>("memopfsf32"),
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!if (!eq (NumElts#EltTypeName, "1f64"), !cast<PatFrag>("memopfsf64"),
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!if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
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!if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
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!if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
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!if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)))));
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// The corresponding float type, e.g. v16f32 for v16i32
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// Note: For EltSize < 32, FloatVT is illegal and TableGen
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@ -114,6 +120,10 @@ def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
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def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
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def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
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// the scalar staff
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def f32x_info : X86VectorVTInfo<1, f32, VR128X, "ss">;
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def f64x_info : X86VectorVTInfo<1, f64, VR128X, "sd">;
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class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
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X86VectorVTInfo i128> {
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X86VectorVTInfo info512 = i512;
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@ -183,7 +193,7 @@ multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
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string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, dag MaskingRHS,
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string Round = "",
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SDNode Select = vselect, string Round = "",
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string MaskingConstraint = "",
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InstrItinClass itin = NoItinerary,
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bit IsCommutable = 0> :
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@ -192,11 +202,11 @@ multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
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[(set _.RC:$dst, RHS)],
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[(set _.RC:$dst, MaskingRHS)],
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[(set _.RC:$dst,
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(vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
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(Select _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
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Round, MaskingConstraint, NoItinerary, IsCommutable>;
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// This multiclass generates the unconditional/non-masking, the masking and
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// the zero-masking variant of the instruction. In the masking case, the
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// the zero-masking variant of the vector instruction. In the masking case, the
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// perserved vector elements come from a new dummy input operand tied to $dst.
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multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins, string OpcodeStr,
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@ -208,8 +218,23 @@ multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
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!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
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!con((ins _.KRCWM:$mask), Ins),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(vselect _.KRCWM:$mask, RHS, _.RC:$src0), Round,
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"$src0 = $dst", itin, IsCommutable>;
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(vselect _.KRCWM:$mask, RHS, _.RC:$src0), vselect,
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Round, "$src0 = $dst", itin, IsCommutable>;
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// This multiclass generates the unconditional/non-masking, the masking and
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// the zero-masking variant of the scalar instruction.
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multiclass AVX512_maskable_scalar<bits<8> O, Format F, X86VectorVTInfo _,
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dag Outs, dag Ins, string OpcodeStr,
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string AttSrcAsm, string IntelSrcAsm,
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dag RHS, string Round = "",
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InstrItinClass itin = NoItinerary,
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bit IsCommutable = 0> :
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AVX512_maskable_common<O, F, _, Outs, Ins,
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!con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
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!con((ins _.KRCWM:$mask), Ins),
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OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
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(X86select _.KRCWM:$mask, RHS, _.RC:$src0), X86select,
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Round, "$src0 = $dst", itin, IsCommutable>;
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// Similar to AVX512_maskable but in this case one of the source operands
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// ($src1) is already tied to $dst so we just use that for the preserved
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@ -4190,60 +4215,40 @@ def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
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(VRCP14PDZr VR512:$src)>;
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/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
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multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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X86MemOperand x86memop> {
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let hasSideEffects = 0, Predicates = [HasERI] in {
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def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
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def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
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[]>, EVEX_4V, EVEX_B;
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let mayLoad = 1 in {
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
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}
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}
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multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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SDNode OpNode> {
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defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 FROUND_CURRENT))>;
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defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
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defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(OpNode (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
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(i32 FROUND_CURRENT))>;
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}
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defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
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EVEX_CD8<32, CD8VT1>;
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defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
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VEX_W, EVEX_CD8<64, CD8VT1>;
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defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
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EVEX_CD8<32, CD8VT1>;
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defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
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VEX_W, EVEX_CD8<64, CD8VT1>;
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def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
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(v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
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FROUND_NO_EXC)),
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(COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
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(COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
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def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
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(v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
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FROUND_NO_EXC)),
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(COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
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(COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
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def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
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(v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
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FROUND_NO_EXC)),
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(COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
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(COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
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def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
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(v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
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FROUND_NO_EXC)),
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(COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
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(COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
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multiclass avx512_eri_s<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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defm SS : avx512_fp28_s<opc, OpcodeStr#"ss", f32x_info, OpNode>,
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EVEX_CD8<32, CD8VT1>;
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defm SD : avx512_fp28_s<opc, OpcodeStr#"sd", f64x_info, OpNode>,
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EVEX_CD8<64, CD8VT1>, VEX_W;
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}
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let hasSideEffects = 0, Predicates = [HasERI] in {
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defm VRCP28 : avx512_eri_s<0xCB, "vrcp28", X86rcp28s>, T8PD, EVEX_4V;
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defm VRSQRT28 : avx512_eri_s<0xCD, "vrsqrt28", X86rsqrt28s>, T8PD, EVEX_4V;
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}
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/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
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multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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@ -4256,12 +4261,14 @@ multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src), OpcodeStr,
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"$src", "$src",
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(OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)), "{sae}">, EVEX_B;
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(OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC)),
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"{sae}">, EVEX_B;
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defm m : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.MemOp:$src), OpcodeStr, "$src", "$src",
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(OpNode (_.FloatVT
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(bitconvert (_.LdFrag addr:$src))), (i32 FROUND_CURRENT))>;
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(bitconvert (_.LdFrag addr:$src))),
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(i32 FROUND_CURRENT))>;
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defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.MemOp:$src), OpcodeStr, "$src", "$src",
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@ -205,6 +205,8 @@ def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
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SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
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def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
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SDTCisVec<0>, SDTCisInt<2>]>;
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def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
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SDTCisVec<0>, SDTCisInt<3>]>;
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def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
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def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
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@ -265,7 +267,10 @@ def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
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def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
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def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
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def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
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def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
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def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
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def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
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def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
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SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
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@ -21,7 +21,7 @@ enum IntrinsicType {
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GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, ADX,
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INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP,
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CMP_MASK, CMP_MASK_CC, VSHIFT, VSHIFT_MASK, COMI,
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INTR_TYPE_1OP_MASK_RM, INTR_TYPE_2OP_MASK
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INTR_TYPE_1OP_MASK_RM, INTR_TYPE_2OP_MASK, INTR_TYPE_SCALAR_MASK_RM
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};
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struct IntrinsicData {
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@ -221,8 +221,12 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_mask_ucmp_w_512, CMP_MASK_CC, X86ISD::CMPMU, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_sd, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rcp28_ss, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RCP28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_sd, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx512_rsqrt28_ss, INTR_TYPE_SCALAR_MASK_RM,X86ISD::RSQRT28, 0),
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X86_INTRINSIC_DATA(avx_hadd_pd_256, INTR_TYPE_2OP, X86ISD::FHADD, 0),
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X86_INTRINSIC_DATA(avx_hadd_ps_256, INTR_TYPE_2OP, X86ISD::FHADD, 0),
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X86_INTRINSIC_DATA(avx_hsub_pd_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0),
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@ -64,16 +64,53 @@ define <8 x double> @test_exp2_pd_512(<8 x double> %a0) {
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declare <8 x double> @llvm.x86.avx512.exp2.pd(<8 x double>, <8 x double>, i8, i32) nounwind readnone
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define <4 x float> @test_rsqrt28_ss(<4 x float> %a0) {
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; CHECK: vrsqrt28ss {sae}, {{.*}}encoding: [0x62,0xf2,0x7d,0x18,0xcd,0xc0]
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; CHECK: vrsqrt28ss %xmm0, %xmm0, %xmm0 {sae} # encoding: [0x62,0xf2,0x7d,0x18,0xcd,0xc0]
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%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
|
||||
|
||||
define <4 x float> @test_rcp28_ss(<4 x float> %a0) {
|
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; CHECK: vrcp28ss {sae}, {{.*}}encoding: [0x62,0xf2,0x7d,0x18,0xcb,0xc0]
|
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; CHECK: vrcp28ss %xmm0, %xmm0, %xmm0 {sae} # encoding: [0x62,0xf2,0x7d,0x18,0xcb,0xc0]
|
||||
%res = call <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 -1, i32 8) ; <<4 x float>> [#uses=1]
|
||||
ret <4 x float> %res
|
||||
}
|
||||
declare <4 x float> @llvm.x86.avx512.rcp28.ss(<4 x float>, <4 x float>, <4 x float>, i8, i32) nounwind readnone
|
||||
|
||||
define <4 x float> @test_rsqrt28_ss_maskz(<4 x float> %a0) {
|
||||
; CHECK: vrsqrt28ss %xmm0, %xmm0, %xmm0 {%k1} {z}{sae} # encoding: [0x62,0xf2,0x7d,0x99,0xcd,0xc0]
|
||||
%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %a0, <4 x float> zeroinitializer, i8 7, i32 8) ;
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define <4 x float> @test_rsqrt28_ss_mask(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0) {
|
||||
; CHECK: vrsqrt28ss %xmm1, %xmm0, %xmm2 {%k1}{sae} # encoding: [0x62,0xf2,0x7d,0x19,0xcd,0xd1]
|
||||
%res = call <4 x float> @llvm.x86.avx512.rsqrt28.ss(<4 x float> %a0, <4 x float> %b0, <4 x float> %c0, i8 7, i32 8) ;
|
||||
ret <4 x float> %res
|
||||
}
|
||||
|
||||
define <2 x double> @test_rsqrt28_sd_maskz(<2 x double> %a0) {
|
||||
; CHECK: vrsqrt28sd %xmm0, %xmm0, %xmm0 {%k1} {z}{sae} # encoding: [0x62,0xf2,0xfd,0x99,0xcd,0xc0]
|
||||
%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %a0, <2 x double> zeroinitializer, i8 7, i32 8) ;
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double>, <2 x double>, <2 x double>, i8, i32) nounwind readnone
|
||||
|
||||
define <2 x double> @test_rsqrt28_sd_maskz_mem(<2 x double> %a0, double* %ptr ) {
|
||||
; CHECK: vrsqrt28sd (%rdi), %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0xcd,0x07]
|
||||
%mem = load double * %ptr, align 8
|
||||
%mem_v = insertelement <2 x double> undef, double %mem, i32 0
|
||||
%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ;
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
define <2 x double> @test_rsqrt28_sd_maskz_mem_offset(<2 x double> %a0, double* %ptr ) {
|
||||
; CHECK: vrsqrt28sd 144(%rdi), %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0xcd,0x47,0x12]
|
||||
%ptr1 = getelementptr double* %ptr, i32 18
|
||||
%mem = load double * %ptr1, align 8
|
||||
%mem_v = insertelement <2 x double> undef, double %mem, i32 0
|
||||
%res = call <2 x double> @llvm.x86.avx512.rsqrt28.sd(<2 x double> %a0, <2 x double> %mem_v, <2 x double> zeroinitializer, i8 7, i32 4) ;
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user