mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Replace some assert(0)'s with llvm_unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211141 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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868e579be6
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10d664fee7
@ -97,7 +97,7 @@ void BitstreamCursor::readAbbreviatedField(const BitCodeAbbrevOp &Op,
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switch (Op.getEncoding()) {
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switch (Op.getEncoding()) {
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case BitCodeAbbrevOp::Array:
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case BitCodeAbbrevOp::Array:
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case BitCodeAbbrevOp::Blob:
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case BitCodeAbbrevOp::Blob:
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assert(0 && "Should not reach here");
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llvm_unreachable("Should not reach here");
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case BitCodeAbbrevOp::Fixed:
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case BitCodeAbbrevOp::Fixed:
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Vals.push_back(Read((unsigned)Op.getEncodingData()));
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Vals.push_back(Read((unsigned)Op.getEncodingData()));
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break;
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break;
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@ -117,7 +117,7 @@ void BitstreamCursor::skipAbbreviatedField(const BitCodeAbbrevOp &Op) {
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switch (Op.getEncoding()) {
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switch (Op.getEncoding()) {
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case BitCodeAbbrevOp::Array:
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case BitCodeAbbrevOp::Array:
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case BitCodeAbbrevOp::Blob:
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case BitCodeAbbrevOp::Blob:
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assert(0 && "Should not reach here");
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llvm_unreachable("Should not reach here");
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case BitCodeAbbrevOp::Fixed:
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case BitCodeAbbrevOp::Fixed:
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(void)Read((unsigned)Op.getEncodingData());
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(void)Read((unsigned)Op.getEncodingData());
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break;
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break;
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@ -1141,7 +1141,7 @@ bool ModuleLinker::linkModuleFlagsMetadata() {
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// Perform the merge for standard behavior types.
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// Perform the merge for standard behavior types.
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switch (SrcBehaviorValue) {
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switch (SrcBehaviorValue) {
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case Module::Require:
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case Module::Require:
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case Module::Override: assert(0 && "not possible"); break;
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case Module::Override: llvm_unreachable("not possible");
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case Module::Error: {
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case Module::Error: {
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// Emit an error if the values differ.
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// Emit an error if the values differ.
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if (SrcOp->getOperand(2) != DstOp->getOperand(2)) {
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if (SrcOp->getOperand(2) != DstOp->getOperand(2)) {
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@ -211,7 +211,7 @@ void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
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const MachineOperand &MO = MI->getOperand(OpNum);
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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switch (MO.getType()) {
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default:
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default:
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assert(0 && "<unknown operand type>");
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llvm_unreachable("<unknown operand type>");
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case MachineOperand::MO_Register: {
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case MachineOperand::MO_Register: {
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unsigned Reg = MO.getReg();
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unsigned Reg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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@ -291,7 +291,7 @@ static bool isConditionalBranch(unsigned Opc) {
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static MachineBasicBlock *getDestBlock(MachineInstr *MI) {
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static MachineBasicBlock *getDestBlock(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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switch (MI->getOpcode()) {
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default:
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default:
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assert(0 && "unexpected opcode!");
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llvm_unreachable("unexpected opcode!");
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case AArch64::TBZW:
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case AArch64::TBZW:
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case AArch64::TBNZW:
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case AArch64::TBNZW:
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case AArch64::TBZX:
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case AArch64::TBZX:
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@ -309,7 +309,7 @@ static MachineBasicBlock *getDestBlock(MachineInstr *MI) {
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static unsigned getOppositeConditionOpcode(unsigned Opc) {
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static unsigned getOppositeConditionOpcode(unsigned Opc) {
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switch (Opc) {
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switch (Opc) {
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default:
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default:
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assert(0 && "unexpected opcode!");
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llvm_unreachable("unexpected opcode!");
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case AArch64::TBNZW: return AArch64::TBZW;
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case AArch64::TBNZW: return AArch64::TBZW;
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case AArch64::TBNZX: return AArch64::TBZX;
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case AArch64::TBNZX: return AArch64::TBZX;
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case AArch64::TBZW: return AArch64::TBNZW;
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case AArch64::TBZW: return AArch64::TBNZW;
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@ -325,7 +325,7 @@ static unsigned getOppositeConditionOpcode(unsigned Opc) {
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static unsigned getBranchDisplacementBits(unsigned Opc) {
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static unsigned getBranchDisplacementBits(unsigned Opc) {
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switch (Opc) {
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switch (Opc) {
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default:
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default:
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assert(0 && "unexpected opcode!");
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llvm_unreachable("unexpected opcode!");
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case AArch64::TBNZW:
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case AArch64::TBNZW:
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case AArch64::TBZW:
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case AArch64::TBZW:
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case AArch64::TBNZX:
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case AArch64::TBNZX:
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@ -2108,7 +2108,7 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
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.getVectorElementType()
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.getVectorElementType()
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.getSizeInBits()) {
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.getSizeInBits()) {
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default:
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default:
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assert(0 && "Unexpected vector element type!");
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llvm_unreachable("Unexpected vector element type!");
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case 64:
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case 64:
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SubReg = AArch64::dsub;
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SubReg = AArch64::dsub;
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break;
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break;
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@ -1273,7 +1273,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
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bool ExtraOp = false;
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bool ExtraOp = false;
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switch (Op.getOpcode()) {
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switch (Op.getOpcode()) {
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default:
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default:
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assert(0 && "Invalid code");
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llvm_unreachable("Invalid code");
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case ISD::ADDC:
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case ISD::ADDC:
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Opc = AArch64ISD::ADDS;
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Opc = AArch64ISD::ADDS;
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break;
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break;
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@ -6674,7 +6674,7 @@ static SDValue tryCombineFixedPointConvert(SDNode *N,
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else if (Vec.getValueType() == MVT::v2i64)
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else if (Vec.getValueType() == MVT::v2i64)
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VecResTy = MVT::v2f64;
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VecResTy = MVT::v2f64;
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else
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else
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assert(0 && "unexpected vector type!");
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llvm_unreachable("unexpected vector type!");
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SDValue Convert =
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SDValue Convert =
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DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
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DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
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@ -1841,7 +1841,7 @@ int llvm::isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
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*OutUnscaledOp = 0;
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*OutUnscaledOp = 0;
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switch (MI.getOpcode()) {
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switch (MI.getOpcode()) {
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default:
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default:
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assert(0 && "unhandled opcode in rewriteAArch64FrameIndex");
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llvm_unreachable("unhandled opcode in rewriteAArch64FrameIndex");
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// Vector spills/fills can't take an immediate offset.
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// Vector spills/fills can't take an immediate offset.
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case AArch64::LD1Twov2d:
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case AArch64::LD1Twov2d:
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case AArch64::LD1Threev2d:
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case AArch64::LD1Threev2d:
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@ -51,7 +51,7 @@ MCOperand AArch64MCInstLower::lowerSymbolOperandDarwin(const MachineOperand &MO,
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AArch64II::MO_PAGEOFF)
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AArch64II::MO_PAGEOFF)
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RefKind = MCSymbolRefExpr::VK_GOTPAGEOFF;
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RefKind = MCSymbolRefExpr::VK_GOTPAGEOFF;
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else
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else
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assert(0 && "Unexpected target flags with MO_GOT on GV operand");
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llvm_unreachable("Unexpected target flags with MO_GOT on GV operand");
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} else if ((MO.getTargetFlags() & AArch64II::MO_TLS) != 0) {
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} else if ((MO.getTargetFlags() & AArch64II::MO_TLS) != 0) {
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if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_PAGE)
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if ((MO.getTargetFlags() & AArch64II::MO_FRAGMENT) == AArch64II::MO_PAGE)
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RefKind = MCSymbolRefExpr::VK_TLVPPAGE;
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RefKind = MCSymbolRefExpr::VK_TLVPPAGE;
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@ -154,7 +154,7 @@ bool AArch64MCInstLower::lowerOperand(const MachineOperand &MO,
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MCOperand &MCOp) const {
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MCOperand &MCOp) const {
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switch (MO.getType()) {
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switch (MO.getType()) {
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default:
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default:
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assert(0 && "unknown operand type");
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llvm_unreachable("unknown operand type");
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case MachineOperand::MO_Register:
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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if (MO.isImplicit())
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@ -918,7 +918,7 @@ void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
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else
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else
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O << getRegisterName(Reg);
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O << getRegisterName(Reg);
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} else
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} else
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assert(0 && "unknown operand kind in printPostIncOperand64");
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llvm_unreachable("unknown operand kind in printPostIncOperand64");
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}
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}
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void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
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void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
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@ -1109,7 +1109,7 @@ static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
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while (Stride--) {
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while (Stride--) {
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switch (Reg) {
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switch (Reg) {
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default:
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default:
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assert(0 && "Vector register expected!");
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llvm_unreachable("Vector register expected!");
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case AArch64::Q0: Reg = AArch64::Q1; break;
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case AArch64::Q0: Reg = AArch64::Q1; break;
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case AArch64::Q1: Reg = AArch64::Q2; break;
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case AArch64::Q1: Reg = AArch64::Q2; break;
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case AArch64::Q2: Reg = AArch64::Q3; break;
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case AArch64::Q2: Reg = AArch64::Q3; break;
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@ -86,7 +86,7 @@ public:
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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switch (Kind) {
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default:
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default:
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assert(0 && "Unknown fixup kind!");
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llvm_unreachable("Unknown fixup kind!");
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case AArch64::fixup_aarch64_tlsdesc_call:
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case AArch64::fixup_aarch64_tlsdesc_call:
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return 0;
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return 0;
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@ -75,7 +75,7 @@ bool AArch64MachObjectWriter::getAArch64FixupKindMachOInfo(
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Log2Size = llvm::Log2_32(4);
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Log2Size = llvm::Log2_32(4);
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switch (Sym->getKind()) {
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switch (Sym->getKind()) {
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default:
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default:
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assert(0 && "Unexpected symbol reference variant kind!");
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llvm_unreachable("Unexpected symbol reference variant kind!");
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case MCSymbolRefExpr::VK_PAGEOFF:
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case MCSymbolRefExpr::VK_PAGEOFF:
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RelocType = unsigned(MachO::ARM64_RELOC_PAGEOFF12);
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RelocType = unsigned(MachO::ARM64_RELOC_PAGEOFF12);
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return true;
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return true;
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@ -493,7 +493,7 @@ def neon_vcvt_imm32 : Operand<i32> {
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// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
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// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
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def rot_imm_XFORM: SDNodeXForm<imm, [{
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def rot_imm_XFORM: SDNodeXForm<imm, [{
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switch (N->getZExtValue()){
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switch (N->getZExtValue()){
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default: assert(0);
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default: llvm_unreachable(nullptr);
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case 0: return CurDAG->getTargetConstant(0, MVT::i32);
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case 0: return CurDAG->getTargetConstant(0, MVT::i32);
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case 8: return CurDAG->getTargetConstant(1, MVT::i32);
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case 8: return CurDAG->getTargetConstant(1, MVT::i32);
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case 16: return CurDAG->getTargetConstant(2, MVT::i32);
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case 16: return CurDAG->getTargetConstant(2, MVT::i32);
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@ -220,7 +220,7 @@ public:
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void recordCPEClone(unsigned CPIdx, unsigned CPCloneIdx) {
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void recordCPEClone(unsigned CPIdx, unsigned CPCloneIdx) {
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if (!CPEClones.insert(std::make_pair(CPCloneIdx, CPIdx)).second)
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if (!CPEClones.insert(std::make_pair(CPCloneIdx, CPIdx)).second)
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assert(0 && "Duplicate entries!");
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llvm_unreachable("Duplicate entries!");
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}
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}
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unsigned getOriginalCPIdx(unsigned CloneIdx) const {
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unsigned getOriginalCPIdx(unsigned CloneIdx) const {
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@ -1438,7 +1438,7 @@ void NVPTXAsmPrinter::printModuleLevelGV(const GlobalVariable *GVar,
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O << "linear";
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O << "linear";
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break;
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break;
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case 2:
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case 2:
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assert(0 && "Anisotropic filtering is not supported");
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llvm_unreachable("Anisotropic filtering is not supported");
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default:
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default:
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O << "nearest";
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O << "nearest";
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break;
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break;
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@ -1562,7 +1562,7 @@ void NVPTXAsmPrinter::printModuleLevelGV(const GlobalVariable *GVar,
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}
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}
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break;
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break;
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default:
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default:
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assert(0 && "type not supported yet");
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llvm_unreachable("type not supported yet");
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}
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}
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}
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}
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@ -1682,7 +1682,7 @@ void NVPTXAsmPrinter::emitPTXGlobalVariable(const GlobalVariable *GVar,
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O << "]";
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O << "]";
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break;
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break;
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default:
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default:
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assert(0 && "type not supported yet");
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llvm_unreachable("type not supported yet");
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}
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}
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return;
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return;
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}
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}
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@ -330,7 +330,7 @@ public:
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unsigned Reg = Op.getReg();
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unsigned Reg = Op.getReg();
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unsigned regIdx = 0;
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unsigned regIdx = 0;
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switch (Op.Reg.Kind) {
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switch (Op.Reg.Kind) {
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default: assert(0 && "Unexpected register kind!");
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default: llvm_unreachable("Unexpected register kind!");
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case rk_FloatReg:
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case rk_FloatReg:
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regIdx = Reg - Sparc::F0;
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regIdx = Reg - Sparc::F0;
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if (regIdx % 4 || regIdx > 31)
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if (regIdx % 4 || regIdx > 31)
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@ -201,7 +201,7 @@ namespace {
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}
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}
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
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// FIXME.
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// FIXME.
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assert(0 && "relaxInstruction() unimplemented");
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llvm_unreachable("relaxInstruction() unimplemented");
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}
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}
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
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@ -124,7 +124,7 @@ SparcMCExpr::VariantKind SparcMCExpr::parseVariantKind(StringRef name)
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Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
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Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) {
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switch (Kind) {
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switch (Kind) {
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default: assert(0 && "Unhandled SparcMCExpr::VariantKind");
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default: llvm_unreachable("Unhandled SparcMCExpr::VariantKind");
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case VK_Sparc_LO: return Sparc::fixup_sparc_lo10;
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case VK_Sparc_LO: return Sparc::fixup_sparc_lo10;
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case VK_Sparc_HI: return Sparc::fixup_sparc_hi22;
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case VK_Sparc_HI: return Sparc::fixup_sparc_hi22;
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case VK_Sparc_H44: return Sparc::fixup_sparc_h44;
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case VK_Sparc_H44: return Sparc::fixup_sparc_h44;
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@ -213,7 +213,8 @@ extern "C" void *SparcCompilationCallbackC(intptr_t StubAddr) {
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void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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assert(0 && "FIXME: Implement SparcJITInfo::replaceMachineCodeForFunction");
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llvm_unreachable("FIXME: Implement SparcJITInfo::"
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"replaceMachineCodeForFunction");
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}
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}
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@ -380,7 +380,7 @@ static void ComputeFixedEncoding(const CodeGenIntrinsic &Int,
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case 3: TypeSig.push_back(IIT_STRUCT3); break;
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case 3: TypeSig.push_back(IIT_STRUCT3); break;
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case 4: TypeSig.push_back(IIT_STRUCT4); break;
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case 4: TypeSig.push_back(IIT_STRUCT4); break;
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case 5: TypeSig.push_back(IIT_STRUCT5); break;
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case 5: TypeSig.push_back(IIT_STRUCT5); break;
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default: assert(0 && "Unhandled case in struct");
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default: llvm_unreachable("Unhandled case in struct");
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}
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}
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for (unsigned i = 0, e = Int.IS.RetVTs.size(); i != e; ++i)
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for (unsigned i = 0, e = Int.IS.RetVTs.size(); i != e; ++i)
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