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Basic FastISel support for floating-point constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -20,6 +20,7 @@
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namespace llvm {
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class ConstantFP;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineRegisterInfo;
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@ -93,6 +94,15 @@ protected:
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ISD::NodeType Opcode,
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unsigned Op0, uint64_t Imm);
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/// FastEmit_rf - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and floating-point immediate operands be emitted.
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///
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virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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unsigned Op0, ConstantFP *FPImm);
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/// FastEmit_rri - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// register and immediate operands be emitted.
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@ -111,6 +121,15 @@ protected:
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unsigned Op0, uint64_t Imm,
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MVT::SimpleValueType ImmType);
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/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
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/// to emit an instruction with an immediate operand using FastEmit_rf.
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/// If that fails, it materializes the immediate into a register and try
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/// FastEmit_rr instead.
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unsigned FastEmit_rf_(MVT::SimpleValueType VT,
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ISD::NodeType Opcode,
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unsigned Op0, ConstantFP *FPImm,
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MVT::SimpleValueType ImmType);
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/// FastEmit_i - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// immediate operand be emitted.
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@ -119,6 +138,14 @@ protected:
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ISD::NodeType Opcode,
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uint64_t Imm);
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/// FastEmit_f - This method is called by target-independent code
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/// to request that an instruction with the given type, opcode, and
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/// floating-point immediate operand be emitted.
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virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
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MVT::SimpleValueType RetVT,
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ISD::NodeType Opcode,
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ConstantFP *FPImm);
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/// FastEmitInst_ - Emit a MachineInstr with no operands and a
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/// result register in the given register class.
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///
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@ -146,6 +173,13 @@ protected:
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const TargetRegisterClass *RC,
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unsigned Op0, uint64_t Imm);
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/// FastEmitInst_rf - Emit a MachineInstr with two register operands
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/// and a result register in the given register class.
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///
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unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
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const TargetRegisterClass *RC,
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unsigned Op0, ConstantFP *FPImm);
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/// FastEmitInst_rri - Emit a MachineInstr with two register operands,
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/// an immediate, and a result register in the given register class.
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///
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