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AVX-512: blank lines, duplicated tests, no functional changes
see comments http://reviews.llvm.org/D6835 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233528 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3743,16 +3743,19 @@ multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.ScalarMemOp:$src3),
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(ins _.RC:$src2, _.ScalarMemOp:$src3),
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OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"), !strconcat("$src2, ${src3}", _.BroadcastStr ),
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OpcodeStr, !strconcat("${src3}", _.BroadcastStr,", $src2"),
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(OpNode _.RC:$src1, _.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
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!strconcat("$src2, ${src3}", _.BroadcastStr ),
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(OpNode _.RC:$src1,
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_.RC:$src2,(_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3))))>,
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AVX512FMA3Base, EVEX_B;
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AVX512FMA3Base, EVEX_B;
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}
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}
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} // Constraints = "$src1 = $dst"
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} // Constraints = "$src1 = $dst"
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst" in {
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// Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
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// Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
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multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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multiclass avx512_fma3_round_rrb<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode> {
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X86VectorVTInfo _,
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SDPatternOperator OpNode> {
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defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
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@ -3772,7 +3775,6 @@ multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
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SDPatternOperator OpNode> {
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SDPatternOperator OpNode> {
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defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
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defm v213r : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
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VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
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VTI, OpNode>, EVEX_CD8<VTI.EltSize, CD8VF>;
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defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
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defm v231r : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
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VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
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VTI>, EVEX_CD8<VTI.EltSize, CD8VF>;
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}
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}
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@ -3794,12 +3796,14 @@ let ExeDomain = SSEPackedSingle in {
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let ExeDomain = SSEPackedDouble in {
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let ExeDomain = SSEPackedDouble in {
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defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
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defm NAME##PDZ : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
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v8f64_info, OpNode>,
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v8f64_info, OpNode>,
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avx512_fma3_round_forms<opc213, OpcodeStr,
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avx512_fma3_round_forms<opc213, OpcodeStr, v8f64_info,
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v8f64_info, OpNodeRnd>, EVEX_V512, VEX_W;
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OpNodeRnd>, EVEX_V512, VEX_W;
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defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
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defm NAME##PDZ256 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
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v4f64x_info, OpNode>, EVEX_V256, VEX_W;
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v4f64x_info, OpNode>,
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EVEX_V256, VEX_W;
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defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
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defm NAME##PDZ128 : avx512_fma3p_forms<opc213, opc231, OpcodeStr,
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v2f64x_info, OpNode>, EVEX_V128, VEX_W;
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v2f64x_info, OpNode>,
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EVEX_V128, VEX_W;
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}
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}
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}
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}
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@ -3830,26 +3834,29 @@ multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
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}
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}
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} // Constraints = "$src1 = $dst"
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} // Constraints = "$src1 = $dst"
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multiclass avx512_fma3p_m132_f<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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multiclass avx512_fma3p_m132_f<bits<8> opc,
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string OpcodeStr,
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SDNode OpNode> {
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let ExeDomain = SSEPackedSingle in {
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let ExeDomain = SSEPackedSingle in {
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defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
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defm NAME##PSZ : avx512_fma3p_m132<opc, OpcodeStr##ps,
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OpNode,v16f32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
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OpNode,v16f32_info>, EVEX_V512,
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EVEX_CD8<32, CD8VF>;
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defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
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defm NAME##PSZ256 : avx512_fma3p_m132<opc, OpcodeStr##ps,
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OpNode, v8f32x_info>, EVEX_V256, EVEX_CD8<32, CD8VF>;
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OpNode, v8f32x_info>, EVEX_V256,
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EVEX_CD8<32, CD8VF>;
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defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
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defm NAME##PSZ128 : avx512_fma3p_m132<opc, OpcodeStr##ps,
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OpNode, v4f32x_info>, EVEX_V128, EVEX_CD8<32, CD8VF>;
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OpNode, v4f32x_info>, EVEX_V128,
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EVEX_CD8<32, CD8VF>;
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}
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}
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let ExeDomain = SSEPackedDouble in {
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let ExeDomain = SSEPackedDouble in {
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defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
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defm NAME##PDZ : avx512_fma3p_m132<opc, OpcodeStr##pd,
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OpNode, v8f64_info>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VF>;
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OpNode, v8f64_info>, EVEX_V512,
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VEX_W, EVEX_CD8<32, CD8VF>;
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defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
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defm NAME##PDZ256 : avx512_fma3p_m132<opc, OpcodeStr##pd,
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OpNode, v4f64x_info>, EVEX_V256, VEX_W, EVEX_CD8<32, CD8VF>;
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OpNode, v4f64x_info>, EVEX_V256,
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VEX_W, EVEX_CD8<32, CD8VF>;
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defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
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defm NAME##PDZ128 : avx512_fma3p_m132<opc, OpcodeStr##pd,
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OpNode, v2f64x_info>, EVEX_V128, VEX_W, EVEX_CD8<32, CD8VF>;
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OpNode, v2f64x_info>, EVEX_V128,
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VEX_W, EVEX_CD8<32, CD8VF>;
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}
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}
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}
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}
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@ -3860,7 +3867,6 @@ defm VFMSUBADD132 : avx512_fma3p_m132_f<0x97, "vfmsubadd132", X86Fmsubadd>;
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defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
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defm VFNMADD132 : avx512_fma3p_m132_f<0x9C, "vfnmadd132", X86Fnmadd>;
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defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
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defm VFNMSUB132 : avx512_fma3p_m132_f<0x9E, "vfnmsub132", X86Fnmsub>;
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// Scalar FMA
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// Scalar FMA
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let Constraints = "$src1 = $dst" in {
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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@ -3883,7 +3889,6 @@ multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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(OpVT (OpNode RC:$src2, RC:$src1,
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(OpVT (OpNode RC:$src2, RC:$src1,
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(mem_frag addr:$src3))))]>;
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(mem_frag addr:$src3))))]>;
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}
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}
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} // Constraints = "$src1 = $dst"
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} // Constraints = "$src1 = $dst"
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defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
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defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
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@ -3920,6 +3925,7 @@ let hasSideEffects = 0 in {
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EVEX_4V;
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EVEX_4V;
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} // hasSideEffects = 0
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} // hasSideEffects = 0
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}
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}
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let Predicates = [HasAVX512] in {
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let Predicates = [HasAVX512] in {
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defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
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defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
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XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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@ -1,50 +1,8 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding | FileCheck %s
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define <16 x float> @test_x86_vfmadd_ps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
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declare <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
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; CHECK-LABEL: test_x86_vfmadd_ps_z
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; CHECK: vfmadd213ps %zmm
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%res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone
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define <16 x float> @test_mask_vfmadd_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
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; CHECK-LABEL: test_mask_vfmadd_ps
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; CHECK: vfmadd213ps %zmm
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%res = call <16 x float> @llvm.x86.fma.mask.vfmadd.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
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ret <16 x float> %res
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}
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define <8 x double> @test_x86_vfmadd_pd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
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; CHECK-LABEL: test_x86_vfmadd_pd_z
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; CHECK: vfmadd213pd %zmm
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%res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2, i8 -1, i32 4) nounwind
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ret <8 x double> %res
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}
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define <8 x double> @test_mask_fmadd_pd(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
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; CHECK-LABEL: test_mask_fmadd_pd:
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; CHECK: vfmadd213pd %zmm2, %zmm1, %zmm0 {%k1} ## encoding: [0x62,0xf2,0xf5,0x49,0xa8,0xc2]
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%res = call <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask, i32 4)
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ret <8 x double> %res
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}
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declare <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
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declare <8 x double> @llvm.x86.fma.mask.vfmadd.pd.512(<8 x double>, <8 x double>, <8 x double>, i8, i32)
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declare <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32)
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define <16 x float> @test_x86_vfmsubps_z(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2) {
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; CHECK-LABEL: test_x86_vfmsubps_z
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; CHECK: vfmsub213ps %zmm
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%res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 -1, i32 4) nounwind
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float>, <16 x float>, <16 x float>, i16, i32) nounwind readnone
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define <16 x float> @test_mask_vfmsub_ps(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask) {
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; CHECK-LABEL: test_mask_vfmsub_ps
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; CHECK: vfmsub213ps %zmm
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%res = call <16 x float> @llvm.x86.fma.mask.vfmsub.ps.512(<16 x float> %a0, <16 x float> %a1, <16 x float> %a2, i16 %mask, i32 4) nounwind
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ret <16 x float> %res
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}
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define <8 x double> @test_x86_vfmsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
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define <8 x double> @test_x86_vfmsubpd_z(<8 x double> %a0, <8 x double> %a1, <8 x double> %a2) {
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; CHECK-LABEL: test_x86_vfmsubpd_z
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; CHECK-LABEL: test_x86_vfmsubpd_z
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