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[XCore] Remove '-' from back branch asm syntax.

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Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-05-05 13:20:22 +00:00
parent e210df20d3
commit 1114b0ec15
2 changed files with 18 additions and 6 deletions
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9
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -97,6 +97,9 @@ static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
static DecodeStatus Decode2RInstruction(MCInst &Inst, static DecodeStatus Decode2RInstruction(MCInst &Inst,
unsigned Insn, unsigned Insn,
uint64_t Address, uint64_t Address,
@ -239,6 +242,12 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
return MCDisassembler::Success;
}
static DecodeStatus static DecodeStatus
Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
unsigned Combined = fieldFromInstruction(Insn, 6, 5); unsigned Combined = fieldFromInstruction(Insn, 6, 5);

15
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -170,6 +170,9 @@ def ldawb : PatFrag<(ops node:$addr, node:$offset),
// Instruction operand types // Instruction operand types
def calltarget : Operand<i32>; def calltarget : Operand<i32>;
def brtarget : Operand<OtherVT>; def brtarget : Operand<OtherVT>;
def brtarget_neg : Operand<OtherVT> {
let DecoderMethod = "DecodeNegImmOperand";
}
// Addressing modes // Addressing modes
def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
@ -267,10 +270,10 @@ multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
} }
multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
!strconcat(OpcStr, " $a, -$b"), []>; !strconcat(OpcStr, " $a, $b"), []>;
def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget_neg:$b),
!strconcat(OpcStr, " $a, -$b"), []>; !strconcat(OpcStr, " $a, $b"), []>;
} }
multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> { multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
@ -608,9 +611,9 @@ let Uses = [R11], isCall=1 in
defm BLAT : FU6_LU6_np<0b0111001101, "blat">; defm BLAT : FU6_LU6_np<0b0111001101, "blat">;
let isBranch = 1, isTerminator = 1, isBarrier = 1 in { let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget_neg:$a), "bu $a", []>;
def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;