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Teach SimplifyDemandedBits how to look through fpext and fptrunc to simplify their operand

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160823 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Pete Cooper 2012-07-26 22:37:04 +00:00
parent 79ad138a33
commit 1121c786fc
2 changed files with 34 additions and 0 deletions
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6
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@ -1074,6 +1074,12 @@ Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
// like undef&0. The result is known zero, not undef.
UndefElts &= UndefElts2;
break;
case Instruction::FPTrunc:
case Instruction::FPExt:
TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts,
UndefElts, Depth+1);
if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
break;
case Instruction::Call: {
IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);

28
test/Transforms/InstCombine/vec_demanded_elts.ll
View File

@ -162,4 +162,32 @@ entry:
ret <4 x float> %shuffle9.i
}
define <2 x float> @test_fptrunc(double %f) {
; CHECK: @test_fptrunc
; CHECK: insertelement
; CHECK: insertelement
; CHECK-NOT: insertelement
%tmp9 = insertelement <4 x double> undef, double %f, i32 0
%tmp10 = insertelement <4 x double> %tmp9, double 0.000000e+00, i32 1
%tmp11 = insertelement <4 x double> %tmp10, double 0.000000e+00, i32 2
%tmp12 = insertelement <4 x double> %tmp11, double 0.000000e+00, i32 3
%tmp5 = fptrunc <4 x double> %tmp12 to <4 x float>
%ret = shufflevector <4 x float> %tmp5, <4 x float> undef, <2 x i32> <i32 0, i32 1>
ret <2 x float> %ret
}
define <2 x double> @test_fpext(float %f) {
; CHECK: @test_fpext
; CHECK: insertelement
; CHECK: insertelement
; CHECK-NOT: insertelement
%tmp9 = insertelement <4 x float> undef, float %f, i32 0
%tmp10 = insertelement <4 x float> %tmp9, float 0.000000e+00, i32 1
%tmp11 = insertelement <4 x float> %tmp10, float 0.000000e+00, i32 2
%tmp12 = insertelement <4 x float> %tmp11, float 0.000000e+00, i32 3
%tmp5 = fpext <4 x float> %tmp12 to <4 x double>
%ret = shufflevector <4 x double> %tmp5, <4 x double> undef, <2 x i32> <i32 0, i32 1>
ret <2 x double> %ret
}