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Revert r161633-161634 "Partition use lists so defs always come before uses."
These commits broke a number of buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161640 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -150,7 +150,7 @@ private:
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struct { // For MO_Register.
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// Register number is in SmallContents.RegNo.
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MachineOperand *Prev; // Access list for register. See MRI.
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MachineOperand **Prev; // Access list for register.
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MachineOperand *Next;
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} Reg;
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@ -468,6 +468,10 @@ public:
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const TargetRegisterInfo &TRI,
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const TargetInstrInfo &TII);
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private:
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void HandleVRegListReallocation();
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public:
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/// defusechain_iterator - This class provides iterator support for machine
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/// operands in the function that use or define a specific register. If
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/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
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@ -513,20 +517,11 @@ public:
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assert(Op && "Cannot increment end iterator!");
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Op = getNextOperandForReg(Op);
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// All defs come before the uses, so stop def_iterator early.
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if (!ReturnUses) {
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if (Op) {
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if (Op->isUse())
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Op = 0;
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else
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assert(!Op->isDebug() && "Can't have debug defs");
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}
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} else {
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// If this is an operand we don't care about, skip it.
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while (Op && ((!ReturnDefs && Op->isDef()) ||
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(SkipDebug && Op->isDebug())))
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Op = getNextOperandForReg(Op);
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}
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// If this is an operand we don't care about, skip it.
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while (Op && ((!ReturnUses && Op->isUse()) ||
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(!ReturnDefs && Op->isDef()) ||
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(SkipDebug && Op->isDebug())))
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Op = getNextOperandForReg(Op);
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return *this;
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}
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@ -102,9 +102,17 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
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// New virtual register number.
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unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
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// Add a reg, but keep track of whether the vector reallocated or not.
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const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0);
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void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg];
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VRegInfo.grow(Reg);
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VRegInfo[Reg].first = RegClass;
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RegAllocHints.grow(Reg);
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if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase)
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// The vector reallocated, handle this now.
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HandleVRegListReallocation();
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return Reg;
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}
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@ -121,65 +129,55 @@ void MachineRegisterInfo::clearVirtRegs() {
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/// Add MO to the linked list of operands for its register.
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void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
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assert(!MO->isOnRegUseList() && "Already on list");
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MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
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MachineOperand *const Head = HeadRef;
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MachineOperand **Head = &getRegUseDefListHead(MO->getReg());
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// Head points to the first list element.
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// Next is NULL on the last list element.
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// Prev pointers are circular, so Head->Prev == Last.
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// For SSA values, we prefer to keep the definition at the start of the list.
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// we do this by skipping over the definition if it is at the head of the
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// list.
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if (*Head && (*Head)->isDef())
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Head = &(*Head)->Contents.Reg.Next;
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// Head is NULL for an empty list.
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if (!Head) {
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MO->Contents.Reg.Prev = MO;
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MO->Contents.Reg.Next = 0;
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HeadRef = MO;
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return;
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MO->Contents.Reg.Next = *Head;
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if (MO->Contents.Reg.Next) {
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assert(MO->getReg() == MO->Contents.Reg.Next->getReg() &&
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"Different regs on the same list!");
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MO->Contents.Reg.Next->Contents.Reg.Prev = &MO->Contents.Reg.Next;
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}
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assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
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// Insert MO between Last and Head in the circular Prev chain.
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MachineOperand *Last = Head->Contents.Reg.Prev;
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assert(Last && "Inconsistent use list");
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assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
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Head->Contents.Reg.Prev = MO;
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MO->Contents.Reg.Prev = Last;
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// Def operands always precede uses. This allows def_iterator to stop early.
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// Insert def operands at the front, and use operands at the back.
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if (MO->isDef()) {
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// Insert def at the front.
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MO->Contents.Reg.Next = Head;
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HeadRef = MO;
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} else {
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// Insert use at the end.
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MO->Contents.Reg.Next = 0;
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Last->Contents.Reg.Next = MO;
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}
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MO->Contents.Reg.Prev = Head;
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*Head = MO;
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}
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/// Remove MO from its use-def list.
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void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
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assert(MO->isOnRegUseList() && "Operand not on use list");
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MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
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MachineOperand *const Head = HeadRef;
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assert(Head && "List already empty");
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// Unlink this from the doubly linked list of operands.
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MachineOperand *Next = MO->Contents.Reg.Next;
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MachineOperand *Prev = MO->Contents.Reg.Prev;
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// Prev links are circular, next link is NULL instead of looping back to Head.
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if (MO == Head)
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HeadRef = Next;
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else
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Prev->Contents.Reg.Next = Next;
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(Next ? Next : Head)->Contents.Reg.Prev = Prev;
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MachineOperand *NextOp = MO->Contents.Reg.Next;
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*MO->Contents.Reg.Prev = NextOp;
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if (NextOp) {
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assert(NextOp->getReg() == MO->getReg() && "Corrupt reg use/def chain!");
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NextOp->Contents.Reg.Prev = MO->Contents.Reg.Prev;
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}
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MO->Contents.Reg.Prev = 0;
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MO->Contents.Reg.Next = 0;
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}
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/// HandleVRegListReallocation - We just added a virtual register to the
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/// VRegInfo info list and it reallocated. Update the use/def lists info
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/// pointers.
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void MachineRegisterInfo::HandleVRegListReallocation() {
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// The back pointers for the vreg lists point into the previous vector.
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// Update them to point to their correct slots.
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for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
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MachineOperand *List = VRegInfo[Reg].second;
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if (!List) continue;
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// Update the back-pointer to be accurate once more.
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List->Contents.Reg.Prev = &VRegInfo[Reg].second;
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}
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}
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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@ -4,7 +4,7 @@ target triple = "msp430-generic-generic"
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define i8 @mov(i8 %a, i8 %b) nounwind {
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; CHECK: mov:
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; CHECK: mov.{{[bw]}} r14, r15
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; CHECK: mov.b r14, r15
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ret i8 %b
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}
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@ -31,7 +31,7 @@ entry:
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; X64: test3:
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; X64: notl
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; X64: andl
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; X64: shrl
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; X64: shrl %eax
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; X64: ret
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; X32: test3:
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